MCBSTM32EXL Keil, MCBSTM32EXL Datasheet - Page 722
MCBSTM32EXL
Manufacturer Part Number
MCBSTM32EXL
Description
BOARD EVALUATION FOR STM32F103ZE
Manufacturer
Keil
Specifications of MCBSTM32EXL
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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USB on-the-go full-speed (OTG_FS)
26.14.2
722/995
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
Bits 31:20 Reserved
Table 184. Data FIFO (DFIFO) access register map
1. Where x is 3 in device mode and 7 in host mode.
Power and clock gating CSR map
There is a single register for power and clock gating. It is available in both Host and Device
modes.
Table 185. Power and clock gating control and status registers
OTG_FS global registers
These registers are available in both Host and Device modes, and do not need to be
reprogrammed when switching between these modes.
Bit values in the register descriptions are expressed in binary unless otherwise specified.
OTG_FS control and status register (OTG_FS_GOTGCTL)
Address offset: 0x000
Reset value: 0x0000 0800
The OTG control and status register controls the behavior and reflects the status of the OTG
function of the core.
Device IN Endpoint 0/Host OUT Channel 0: DFIFO Write Access
Device OUT Endpoint 0/Host IN Channel 0: DFIFO Read Access
Device IN Endpoint 1/Host OUT Channel 1: DFIFO Write Access
Device OUT Endpoint 1/Host IN Channel 1: DFIFO Read Access
...
Device IN Endpoint x
Device OUT Endpoint x
Power and clock gating control register
Reserved
Reserved
Register name
FIFO access register section
(1)
/Host OUT Channel x
(1)
/Host IN Channel x
r
Doc ID 13902 Rev 9
r
r
r
(1)
(1)
Reserved
: DFIFO Read Access
: DFIFO Write Access
PCGCR
Acronym
rw rw rw
9
0xE00-0xE04
0xE05–0xFFF
Offset address: 0xE00–0xFFF
8
r
0x1000–0x1FFC
0x2000–0x2FFC
...
0xX000h–0xXFFCh
Address range
7
6
Reserved
5
4
3
RM0008
w
r
w
r
...
w
r
2
Access
rw
1
0
r
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