MCBSTM32EXL Keil, MCBSTM32EXL Datasheet - Page 799

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MCBSTM32EXL

Manufacturer Part Number
MCBSTM32EXL
Description
BOARD EVALUATION FOR STM32F103ZE
Manufacturer
Keil
Datasheets

Specifications of MCBSTM32EXL

Lead Free Status / RoHS Status
Lead free / RoHS Compliant
RM0008
else if (TXERR or BBERR or STALL)
else if (CHH)
else if (ACK)
else if (DTERR)
The application is expected to write the requests as and when the Request queue space is
available and until the XFRC interrupt is received.
Mask ACK
}
{
Unmask CHH
Disable Channel
if (TXERR)
}
{
Mask CHH
if (Transfer Done or (Error_count == 3))
else
}
{
Reset Error Count
Mask ACK
}
{
Reset Error Count
}
Bulk and control IN transactions
A typical bulk or control IN pipelined transaction-level operation is shown in
See channel 2 (ch_2). The assumptions are:
{
Increment Error Count
Unmask ACK
}
{
De-allocate Channel
}
{
Re-initialize Channel
}
The application is attempting to receive two maximum-packet-size packets
(transfer size = 1 024 bytes).
The receive FIFO can contain at least one maximum-packet-size packet and two
status DWORDs per packet (72 bytes for FS).
The non-periodic request queue depth = 4.
Doc ID 13902 Rev 9
USB on-the-go full-speed (OTG_FS)
Figure
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273.

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