MCBSTM32EXL Keil, MCBSTM32EXL Datasheet - Page 956

• Manufacturer Part Number: MCBSTM32EXL
• Description: BOARD EVALUATION FOR STM32F103ZE
• Manufacturer: Keil

Specifications of MCBSTM32EXL

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Debug support (DBG)
Note:
29.4.3
956/995
Three control bits allow the configuration of the SWJ-DP pin assignments. These bits are
reset by the System Reset.
●
Table 199. Flexible SWJ-DP pin assignment
When the APB bridge write buffer is full, it takes one extra APB cycle when writing the
AFIO_MAPR register. This is because the deactivation of the JTAGSW pins is done in two
cycles to guarantee a clean level on the nTRST and TCK input signals of the core.
●
●
Internal pull-up and pull-down on JTAG pins
It is necessary to ensure that the JTAG input pins are not floating since they are directly
connected to flip-flops to control the debug mode features. Special care must be taken with
the SWCLK/TCK pin which is directly connected to the clock of some of these flip-flops.
To avoid any uncontrolled I/O levels, the STM32F10xxx embeds internal pull-ups and pull-
downs on JTAG input pins:
●
●
●
●
Full SWJ (JTAG-DP + SW-DP) - Reset State
Full SWJ (JTAG-DP + SW-DP) but without NJTRST
JTAG-DP Disabled and SW-DP Enabled
JTAG-DP Disabled and SW-DP Disabled
AFIO_MAPR (@ 0x40010004 in STM32F10xxx MCU)
–
–
Bit 26:24= SWJ_CFG[2:0]
Set and cleared by software.
These bits are used to configure the number of pins assigned to the SWJ debug port.
The goal is to release as much as possible the number of pins to be used as General
Purpose I/Os if using a small size for the debug port.
The default state after reset is “000” (whole pins assigned for a full JTAG-DP
connection). Only one of the 3 bits can be set (it is forbidden to set more than one bit).
Cycle 1: the JTAGSW input signals to the core are tied to 1 or 0 (to 1 for nTRST, TDI
and TMS, to 0 for TCK)
Cycle 2: the GPI/O controller takes the control signals of the SWJTAG I/O pins (like
controls of direction, pull-up/down, Schmitt trigger activation, etc.).
JNTRST: Internal pull-up
JTDI: Internal pull-up
JTMS/SWDIO: Internal pull-up
TCK/SWCLK: Internal pull-down
READ: APB - No Wait State
WRITE: APB - 1 Wait State if the write buffer of the AHB-APB bridge is full.
Available debug ports
Doc ID 13902 Rev 9
SWDIO
PA13 /
JTMS/
X
X
X
SWCLK
PA14 /
JTCK/
SWJ I/O pin assigned
X
X
X
PA15 /
JTDI
X
X
Released
JTDO
PB3 /
X
X
NJTRST
RM0008
PB4/
X