MCBSTM32EXL Keil, MCBSTM32EXL Datasheet - Page 675

• Manufacturer Part Number: MCBSTM32EXL
• Description: BOARD EVALUATION FOR STM32F103ZE
• Manufacturer: Keil

Specifications of MCBSTM32EXL

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

RM0008
25.3.11
Note:
Apart from this, the communications are similar to what is done in normal USART mode.
The conflicts on the line must be managed by the software (by the use of a centralized
arbiter, for instance). In particular, the transmission is never blocked by hardware and
continue to occur as soon as a data is written in the data register while the TE bit is set.
Smartcard
The Smartcard mode is selected by setting the SCEN bit in the USART_CR3 register. In
smartcard mode, the following bits must be kept cleared:
●
●
Moreover, the CLKEN bit may be set in order to provide a clock to the smartcard.
The Smartcard interface is designed to support asynchronous protocol Smartcards as
defined in the ISO 7816-3 standard. The USART should be configured as:
●
●
It is also possible to choose 0.5 stop bit for receiving but it is recommended to use 1.5 stop
bits for both transmitting and receiving to avoid switching between the two configurations.
Figure 252
error.
Figure 252. ISO 7816-3 asynchronous protocol
When connected to a smartcard, the TX output of the USART drives a bidirectional line that
the smartcard also drives into. To do so, SW_RX must be connected on the same I/O than
TX at product level. The Transmitter output enable TX_EN is asserted during the
transmission of the start bit and the data byte, and is deasserted during the stop bit (weak
pull up), so that the receive can drive the line in case of a parity error. If TX_EN is not used,
TX is driven at high level during the stop bit: Thus the receiver can drive the line as long as
TX is configured in open-drain.
Smartcard is a single wire half duplex communication protocol.
●
LINEN bit in the USART_CR2 register,
HDSEL and IREN bits in the USART_CR3 register.
8 bits plus parity: where M=1 and PCE=1 in the USART_CR1 register
1.5 stop bits when transmitting and receiving : where STOP=’11’ in the USART_CR2
register.
Transmission of data from the transmit shift register is guaranteed to be delayed by a
minimum of 1/2 baud clock. In normal operation a full transmit shift register will start
With Parity error
Without Parity error
shows examples of what can be seen on the data line with and without parity
Start
bit
Start
bit
S
S
Universal synchronous asynchronous receiver transmitter (USART)
0
0
1
1
2
2
Doc ID 13902 Rev 9
3
3
4
4
5
5
6
6
7
7
P
P
Line pulled low
by receiver during stop in
case of parity error
Guard time
Guard time
675/995