MCBSTM32EXL Keil, MCBSTM32EXL Datasheet - Page 964

• Manufacturer Part Number: MCBSTM32EXL
• Description: BOARD EVALUATION FOR STM32F103ZE
• Manufacturer: Keil

Specifications of MCBSTM32EXL

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Debug support (DBG)
Note:
29.8.4
29.8.5
964/995
Note that the SW-DP state machine is inactive until the target reads this ID code.
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Further details of the SW-DP state machine can be found in the Cortex-M3 r1p1 TRM and
the CoreSight Design Kit r1p0 TRM.
DP and AP read/write accesses
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SW-DP registers
Access to these registers are initiated when APnDP=0
Table 205. SW-DP registers
00
00
A(3:2)
The SW-DP state machine is in RESET STATE either after power-on reset, or after the
DP has switched from JTAG to SWD or after the line is high for more than 50 cycles
The SW-DP state machine is in IDLE STATE if the line is low for at least two cycles after
RESET state.
After RESET state, it is mandatory to first enter into an IDLE state AND to perform a
READ access of the DP-SW ID CODE register. Otherwise, the target will issue a
FAULT acknowledge response on another transactions.
Read accesses to the DP are not posted: the target response can be immediate (if
ACK=OK) or can be delayed (if ACK=WAIT).
Read accesses to the AP are posted. This means that the result of the access is
returned on the next transfer. If the next access to be done is NOT an AP access, then
the DP-RDBUFF register must be read to obtain the result.
The READOK flag of the DP-CTRL/STAT register is updated on every AP read access
or RDBUFF read request to know if the AP read access was successful.
The SW-DP implements a write buffer (for both DP or AP writes), that enables it to
accept a write operation even when other transactions are still outstanding. If the write
buffer is full, the target acknowledge response is “WAIT”. With the exception of
IDCODE read or CTRL/STAT read or ABORT write which are accepted even if the write
buffer is full.
Because of the asynchronous clock domains SWCLK and HCLK, two extra SWCLK
cycles are needed after a write transaction (after the parity bit) to make the write
effective internally. These cycles should be applied while driving the line low (IDLE
state)
This is particularly important when writing the CTRL/STAT for a power-up request. If the
next transaction (requiring a power-up) occurs immediately, it will fail.
Read
Write
R/W
CTRLSEL bit
of SELECT
register
Doc ID 13902 Rev 9
IDCODE
ABORT
Register
The manufacturer code is not set to ST
code.
0x1BA01477
Notes
(identifies the SW-DP)
RM0008