MCBSTM32EXL Keil, MCBSTM32EXL Datasheet - Page 924

• Manufacturer Part Number: MCBSTM32EXL
• Description: BOARD EVALUATION FOR STM32F103ZE
• Manufacturer: Keil

Specifications of MCBSTM32EXL

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Ethernet (ETH): media access control (MAC) with DMA controller
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31 30 29 28 27 26 25 24 23 22 21 20 19 18
31 30 29 28 27 26 25 24 23 22
Bits 31:22 Reserved
Bits 20:16 Reserved
Bits 31:18 Reserved
Bits 16:7 Reserved
Bits 4:0 Reserved
Reserved
Ethernet MMC receive interrupt mask register (ETH_MMCRIMR)
Address offset: 0x010C
Reset value: 0x0000 0000
The Ethernet MMC receive interrupt mask register maintains the masks for interrupts
generated when the receive statistic counters reach half their maximum value. (MSB of the
counter is set.) It is a 32-bit wide register.
Ethernet MMC transmit interrupt mask register (ETH_MMCTIMR)
Address offset: 0x0110
Reset value: 0x0000 0000
The Ethernet MMC transmit interrupt mask register maintains the masks for interrupts
generated when the transmit statistic counters reach half their maximum value. (MSB of the
counter is set). It is a 32-bit wide register.
Bit 21 TGFM: Transmitted good frames mask
Bit 17 RGUFM: Received good unicast frames mask
Bit 6 RFAEM: Received frames alignment error mask
Bit 5 RFCEM: Received frame CRC error mask
Reserved
Setting this bit masks the interrupt when the transmitted, good frames, counter reaches half
the maximum value.
Setting this bit masks the interrupt when the received, good unicast frames, counter reaches
half the maximum value.
Setting this bit masks the interrupt when the received frames, with alignment error, counter
reaches half the maximum value.
Setting this bit masks the interrupt when the received frames, with CRC error, counter reaches
half the maximum value.
21
rw
20 19 18 17 16
Reserved
Doc ID 13902 Rev 9
17
rw
16 15 14 13 12 11 10
15
rw
14
rw
13 12 11 10
Reserved
9
9
8
8
Reserved
7
7
rw
6
6
rw
5
5
4
4
3
3
Reserved
RM0008
2
2
1
1
0
0