MCBSTM32EXL Keil, MCBSTM32EXL Datasheet - Page 95

• Manufacturer Part Number: MCBSTM32EXL
• Description: BOARD EVALUATION FOR STM32F103ZE
• Manufacturer: Keil

Specifications of MCBSTM32EXL

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

RM0008
6.3.7
Note:
ADC3
EN
31
15
rw
USAR
T1EN
30
14
rw
Bits 31:16
Bit 15 ADC3EN: ADC 3 interface clock enable
Bit 14 USART1EN: USART1 clock enable
Bit 13 TIM8EN: TIM8 Timer clock enable
Bit 12 SPI1EN: SPI 1 clock enable
Bit 11 TIM1EN: TIM1 Timer clock enable
Bit 10 ADC2EN: ADC 2 interface clock enable
APB2 peripheral clock enable register (RCC_APB2ENR)
Address: 0x18
Reset value: 0x0000 0000
Access: word, half-word and byte access
No wait states, except if the access occurs while an access to a peripheral in the APB2
domain is on going. In this case, wait states are inserted until the access to APB2 peripheral
is finished.
When the peripheral clock is not active, the peripheral register values may not be readable
by software and the returned value is always 0x0.
TIM8
EN
29
13
rw
SPI1
Reserved, always read as 0.
Set and cleared by software.
0: ADC 3 interface clock disabled
1: ADC 3 interface clock enabled
Set and cleared by software.
0: USART1 clock disabled
1: USART1 clock enabled
Set and cleared by software.
0: TIM8 timer clock disabled
1: TIM8 timer clock enabled
Set and cleared by software.
0: SPI 1 clock disabled
1: SPI 1 clock enabled
Set and cleared by software.
0: TIM1 timer clock disabled
1: TIM1 timer clock enabled
Set and cleared by software.
0: ADC 2 interface clock disabled
1: ADC 2 interface clock enabled
EN
28
12
rw
TIM1
EN
27
11
rw
ADC2
EN
26
10
rw
Low-, medium- and high-density reset and clock control (RCC)
ADC1
EN
25
rw
9
Doc ID 13902 Rev 9
IOPG
EN
24
rw
8
Reserved
IOPF
EN
23
rw
7
IOPE
EN
22
rw
6
IOPD
EN
21
rw
5
IOPC
EN
20
rw
4
IOPB
EN
19
rw
3
IOPA
EN
18
rw
2
Res.
17
1
95/995
AFIO
EN
16
rw
0