MCBSTM32EXL Keil, MCBSTM32EXL Datasheet - Page 183

• Manufacturer Part Number: MCBSTM32EXL
• Description: BOARD EVALUATION FOR STM32F103ZE
• Manufacturer: Keil

Specifications of MCBSTM32EXL

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

RM0008
10.3
10.3.1
Figure 22. DMA block diagram in connectivity line devices
1. The DMA2 controller is available only in high-density and connectifity line devices.
2. SPI/I2S3, UART4, TIM5, TIM6, TIM7 and DAC DMA requests are available only in high-density and
3. ADC3, SDIO and TIM8 DMA requests are available only in high-density devices.
DMA functional description
The DMA controller performs direct memory transfer by sharing the system bus with the
Cortex™-M3 core. The DMA request may stop the CPU access to the system bus for some
bus cycles, when the CPU and DMA are targeting the same destination (memory or
peripheral). The bus matrix implements round-robin scheduling, thus ensuring at least half
of the system bus bandwidth (both to memory and peripheral) for the CPU.
DMA transactions
After an event, the peripheral sends a request signal to the DMA Controller. The DMA
controller serves the request depending on the channel priorities. As soon as the DMA
Controller accesses the peripheral, an Acknowledge is sent to the peripheral by the DMA
Controller. The peripheral releases its request as soon as it gets the Acknowledge from the
DMA Controller. Once the request is deasserted by the peripheral, the DMA Controller
connectivity line devices.
DMA1
DMA2
Arbiter
Arbiter
Ethernet MAC
USB OTG FS
AHB Slave
AHB Slave
Cortex-M3
Ch.1
Ch.2
Ch.7
Ch.1
Ch.2
Ch.5
DCode
Sys tem
DMA
Doc ID 13902 Rev 9
ICode
DMA request
DMA request
Reset & clock
control (RCC)
FLITF
Bridge 2
Bridge 1
ADC1
ADC2
USART1
SPI1
TIM1
GPIOA
GPIOB
DMA controller (DMA)
SRAM
GPIOC
GPIOD
GPIOE
APB1
AFIO
EXTI
Flash
DAC
PWR
BKP
CAN1
CAN2
I2C2
I2C1
UART5
UART4
USART3
USART2
SPI3/I2S
SPI2/I2S
WWDG
APB2
IWDG
TIM4
TIM7
TIM6
TIM5
TIM3
TIM2
RTC
183/995
ai15811