MCBSTM32EXL Keil, MCBSTM32EXL Datasheet - Page 246

• Manufacturer Part Number: MCBSTM32EXL
• Description: BOARD EVALUATION FOR STM32F103ZE
• Manufacturer: Keil

Specifications of MCBSTM32EXL

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Digital-to-analog converter (DAC)
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Bits 11:8 MAMP1[3:0]: DAC channel1 mask/amplitude selector
Bits 7:6 WAVE1[1:0]: DAC channel1 noise/triangle wave generation enable
Bits 5:3 TSEL1[2:0]: DAC channel1 trigger selection
Bit 12 DMAEN1: DAC channel1 DMA enable
Bit 2 TEN1: DAC channel1 trigger enable
Bit 1 BOFF1: DAC channel1 output buffer disable
Note: only used if bit TEN1 = 1 (DAC channel1 trigger enabled)
Note: When software trigger is selected, it takes only one APB1 clock cycle for DAC_DHRx to
This bit is set and cleared by software.
0: DAC channel1 DMA mode disabled
1: DAC channel1 DMA mode enabled
These bits are written by software to select mask in wave generation mode or amplitude in
triangle generation mode.
0000: Unmask bit0 of LFSR/ Triangle Amplitude equal to 1
0001: Unmask bits[1:0] of LFSR/ Triangle Amplitude equal to 3
0010: Unmask bits[2:0] of LFSR/ Triangle Amplitude equal to 7
0011: Unmask bits[3:0] of LFSR/ Triangle Amplitude equal to 15
0100: Unmask bits[4:0] of LFSR/ Triangle Amplitude equal to 31
0101: Unmask bits[5:0] of LFSR/ Triangle Amplitude equal to 63
0110: Unmask bits[6:0] of LFSR/ Triangle Amplitude equal to 127
0111: Unmask bits[7:0] of LFSR/ Triangle Amplitude equal to 255
1000: Unmask bits[8:0] of LFSR/ Triangle Amplitude equal to 511
1001: Unmask bits[9:0] of LFSR/ Triangle Amplitude equal to 1023
1010: Unmask bits[10:0] of LFSR/ Triangle Amplitude equal to 2047
 1011: Unmask bits[11:0] of LFSR/ Triangle Amplitude equal to 4095
These bits are set/reset by software.
00: wave generation disabled
01: Noise wave generation enabled
1x: Triangle wave generation enabled
Note: only used if bit TEN1 = 1 (DAC channel1 trigger enabled)
These bits select the external event used to trigger DAC channel1
000: Timer 6 TRGO event
001: Timer 3 TRGO event in connectivity line devices, Timer 8 TRGO in high-density devices
010: Timer 7 TRGO event
011: Timer 5 TRGO event
100: Timer 2 TRGO event
101: Timer 4 TRGO event
110: External line9
111: Software trigger
This bit set and cleared by software to enable/disable DAC channel1 trigger
0: DAC channel1 trigger disabled and data written into DAC_DHRx register is transferred
one APB1 clock cycle later to the DAC_DOR1 register.
1: DAC channel1 trigger enabled and data transfer from DAC_DHRx register is transferred
three APB1 clock cycles later to the DAC_DOR1 register.
This bit set and cleared by software to enable/disable DAC channel1 output buffer.
0: DAC channel1 output buffer enabled
1: DAC channel1 output buffer disabled
DAC_DOR1 register transfer.
Doc ID 13902 Rev 9
RM0008