MCBSTM32EXL Keil, MCBSTM32EXL Datasheet - Page 566

• Manufacturer Part Number: MCBSTM32EXL
• Description: BOARD EVALUATION FOR STM32F103ZE
• Manufacturer: Keil

Specifications of MCBSTM32EXL

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Controller area network (bxCAN)
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Bits 25:24 CODE[1:0]
Bits 22:20
Bits 14:12
Bit 27 TME1
Bit 26 TME0
Bit 23 ABRQ2
Bit 19 TERR2
Bit 18 ALST2
Bit 17 TXOK2
Bit 16 RQCP2
Bit 15 ABRQ1
Bit 11 TERR1
Bit 10 ALST1
Bit 9 TXOK1
This bit is set by hardware when no transmit request is pending for mailbox 1.
This bit is set by hardware when no transmit request is pending for mailbox 0.
In case at least one transmit mailbox is free, the code value is equal to the number of the
next transmit mailbox free.
In case all transmit mailboxes are pending, the code value is equal to the number of the
transmit mailbox with the lowest priority.
Set by software to abort the transmission request for the corresponding mailbox.
Cleared by hardware when the mailbox becomes empty.
Setting this bit has no effect when the mailbox is not pending for transmission.
Reserved, forced by hardware to 0.
This bit is set when the previous TX failed due to an error.
This bit is set when the previous TX failed due to an arbitration lost.
The hardware updates this bit after each transmission attempt.
0: The previous transmission failed
1: The previous transmission was successful
This bit is set by hardware when the transmission request on mailbox 2 has been completed
successfully. Please refer to
Set by hardware when the last request (transmit or abort) has been performed.
Cleared by software writing a “1” or by hardware on transmission request (TXRQ2 set in
CAN_TMID2R register).
Clearing this bit clears all the status bits (TXOK2, ALST2 and TERR2) for Mailbox 2.
Set by software to abort the transmission request for the corresponding mailbox.
Cleared by hardware when the mailbox becomes empty.
Setting this bit has no effect when the mailbox is not pending for transmission.
Reserved, forced by hardware to 0.
This bit is set when the previous TX failed due to an error.
This bit is set when the previous TX failed due to an arbitration lost.
The hardware updates this bit after each transmission attempt.
0: The previous transmission failed
1: The previous transmission was successful
This bit is set by hardware when the transmission request on mailbox 1 has been completed
successfully. Please refer to
:
:
:
:
Transmit mailbox 1 empty
Transmit mailbox 0 empty
:
:
:
:
:
:
:
Arbitration lost for mailbox 2
Arbitration lost for mailbox1
Transmission error of mailbox 2
Transmission error of mailbox1
Transmission OK of mailbox 2
Transmission OK of mailbox1
Request completed mailbox2
Abort request for mailbox 2
Abort request for mailbox 1
:
Mailbox code
Doc ID 13902 Rev 9
Figure
Figure 198
198.
RM0008