MCBSTM32EXL Keil, MCBSTM32EXL Datasheet - Page 963

• Manufacturer Part Number: MCBSTM32EXL
• Description: BOARD EVALUATION FOR STM32F103ZE
• Manufacturer: Keil

Specifications of MCBSTM32EXL

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

RM0008
29.8.3
Table 202. Packet request (8-bits)
Refer to the Cortex-M3 r1p1 TRM for a detailed description of DPACC and APACC registers.
The packet request is always followed by the turnaround time (default 1 bit) where neither
the host nor target drive the line.
Table 203. ACK response (3 bits)
The ACK Response must be followed by a turnaround time only if it is a READ transaction or
if a WAIT or FAULT acknowledge has been received.
Table 204. DATA transfer (33 bits)
The DATA transfer must be followed by a turnaround time only if it is a READ transaction.
SW-DP state machine (Reset, idle states, ID code)
The State Machine of the SW-DP has an internal ID code which identifies the SW-DP. It
follows the JEP-106 standard. This ID code is the default ARM one and is set at
0x1BA01477 (corresponding to Cortex-M3 r1p1).
0..31
0..2
Bit
4:3
Bit
Bit
32
0
1
2
5
6
7
Start
APnDP
RnW
A(3:2)
Parity
Stop
Park
ACK
WDATA or
RDATA
Parity
Name
Name
Name
Doc ID 13902 Rev 9
0: DP Access
1: AP Access
0: Write Request
1: Read Request
Address field of the DP or AP registers (refer to
Single bit parity of preceding bits
0
Not driven by the host. Must be read as “1” by the target
because of the pull-up
001: FAULT
010: WAIT
100: OK
Write or Read data
Single parity of the 32 data bits
Must be “1”
Description
Description
Description
Debug support (DBG)
Table
201)
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