MCBSTM32EXL Keil, MCBSTM32EXL Datasheet - Page 746

• Manufacturer Part Number: MCBSTM32EXL
• Description: BOARD EVALUATION FOR STM32F103ZE
• Manufacturer: Keil

Specifications of MCBSTM32EXL

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

USB on-the-go full-speed (OTG_FS)
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31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
Bits 31:16 Reserved
Bits 23:16 PTXQSAV: Periodic transmit request queue space available
Bits 15:0 HAINT: Channel interrupts
Bits 15:0 PTXFSAVL: Periodic transmit data FIFO space available
OTG_FS Host all channels interrupt register (OTG_FS_HAINT)
Address offset: 0x414
Reset value: 0x0000 000
When a significant event occurs on a channel, the Host all channels interrupt register
interrupts the application using the Host channels interrupt bit of the Core interrupt register
(HCINT bit in OTG_FS_GINTSTS). This is shown in
per channel, up to a maximum of 16 bits. Bits in this register are set and cleared when the
application sets and clears bits in the corresponding Host channel-x interrupt register.
One bit per channel: Bit 0 for Channel 0, bit 15 for Channel 15
Indicates the number of free locations available to be written in the periodic transmit request
queue. This queue holds both IN and OUT requests.
Indicates the number of free locations available to be written to in the periodic TxFIFO.
Values are in terms of 32-bit words
00: Periodic transmit request queue is full
01: dx1 location available
10: dx2 locations available
bxn: dxn locations available (0  dxn  8)
Others: Reserved
0000: Periodic TxFIFO is full
0001: dx1 word available
0010: dx2 words available
bxn: dxn words available (where 0  dxn  dx512)
bx200: dx512 words available
Others: Reserved
Reserved
Doc ID 13902 Rev 9
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268. There is one interrupt bit
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