MCBSTM32EXL Keil, MCBSTM32EXL Datasheet - Page 679

• Manufacturer Part Number: MCBSTM32EXL
• Description: BOARD EVALUATION FOR STM32F103ZE
• Manufacturer: Keil

Specifications of MCBSTM32EXL

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

RM0008
25.3.13
Note:
Note:
Continuous communication using DMA
The USART is capable to continue communication using the DMA. The DMA requests for
Rx buffer and Tx buffer are generated independently.
You should refer to product specs for availability of the DMA controller. If DMA is not
available in the product, you should use the USART as explained in
25.3.3. In the USART_SR register, you can clear the TXE/ RXNE flags to achieve
continuous communication.
Transmission using DMA
DMA mode can be enabled for transmission by setting DMAT bit in the USART_CR3
register. Data is loaded from a SRAM area configured using the DMA peripheral (refer to the
DMA specification) to the USART_DR register whenever the TXE bit is set. To map a DMA
channel for USART transmission, use the following procedure (x denotes the channel
number):
1.
2.
3.
4.
5.
6.
When the number of data transfers programmed in the DMA Controller is reached, the DMA
controller generates an interrupt on the DMA channel interrupt vector. The DMAT bit should
be cleared by software in the USART_CR3 register during the interrupt subroutine.
If DMA is used for transmission, do not enable the TXEIE bit.
Reception using DMA
DMA mode can be enabled for reception by setting the DMAR bit in USART_CR3 register.
Data is loaded from the USART_DR register to a SRAM area configured using the DMA
peripheral (refer to the DMA specification) whenever a data byte is received. To map a DMA
channel for USART reception, use the following procedure:
1.
2.
3.
4.
5.
6.
Write the USART_DR register address in the DMA control register to configure it as the
destination of the transfer. The data will be moved to this address from memory after
each TXE event.
Write the memory address in the DMA control register to configure it as the source of
the transfer. The data will be loaded into the USART_DR register from this memory
area after each TXE event.
Configure the total number of bytes to be transferred to the DMA control register.
Configure the channel priority in the DMA register
Configure DMA interrupt generation after half/ full transfer as required by the
application.
Activate the channel in the DMA register.
Write the USART_DR register address in the DMA control register to configure it as the
source of the transfer. The data will be moved from this address to the memory after
each RXNE event.
Write the memory address in the DMA control register to configure it as the destination
of the transfer. The data will be loaded from USART_DR to this memory area after each
RXNE event.
Configure the total number of bytes to be transferred in the DMA control register.
Configure the channel priority in the DMA control register
Configure interrupt generation after half/ full transfer as required by the application.
Activate the channel in the DMA control register.
Universal synchronous asynchronous receiver transmitter (USART)
Doc ID 13902 Rev 9
Section 25.3.2
or
679/995