MCBSTM32EXL Keil, MCBSTM32EXL Datasheet - Page 875

• Manufacturer Part Number: MCBSTM32EXL
• Description: BOARD EVALUATION FOR STM32F103ZE
• Manufacturer: Keil

Specifications of MCBSTM32EXL

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

RM0008
Figure 307. System time update using the Fine correction method
The system time update logic requires a 50 MHz clock frequency to achieve 20 ns accuracy.
The frequency division is the ratio of the reference clock frequency to the required clock
frequency. Hence, if the reference clock (HCLK) is, let us say, 66 MHz, the ratio is calculated
as 66 MHz/50 MHz = 1.32. Hence, the default addend value to be set in the register is
2
If the reference clock drifts lower, to 65 MHz for example, the ratio is 65/50 or 1.3 and the
value to set in the addend register is 2
higher, to 67 MHz for example, the addend register must be set to 0xBF0 B7672. When the
clock drift is zero, the default addend value of 0xC1F0 7C1F (2
programmed.
In
makes an accuracy of 20 ns in the system time (in other words, it is incremented by 20 ns
steps).
The software has to calculate the drift in frequency based on the Sync messages, and to
update the Addend register accordingly. Initially, the slave clock is set with
FreqCompensationValue0 in the Addend register. This value is as follows:
If MasterToSlaveDelay is initially assumed to be the same for consecutive Sync messages,
the algorithm described below must be applied. After a few Sync cycles, frequency lock
occurs. The slave clock can then determine a precise MasterToSlaveDelay value and re-
synchronize with the master using the new value.
32
Figure
/1.32, which is equal to 0xC1F0 7C1F.
FreqCompensationValue0 = 2
307, the constant value used to increment the subsecond register is 0d43. This
Addend update
Ethernet (ETH): media access control (MAC) with DMA controller
Addend register
Doc ID 13902 Rev 9
Increment Subsecond
register
Increment Second register
32
/ FreqDivisionRatio
Accumulator register
32
+
/1.30 equal to 0xC4EC 4EC4. If the clock drifts
Subsecond register
Second register
Constant value
+
32
/1.32) should be
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