MCBSTM32EXL Keil, MCBSTM32EXL Datasheet - Page 317

• Manufacturer Part Number: MCBSTM32EXL
• Description: BOARD EVALUATION FOR STM32F103ZE
• Manufacturer: Keil

Specifications of MCBSTM32EXL

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

RM0008
13.4.20
13.4.21
Table 74.
Offset
0x0C
0x00
0x04
0x08
0x10
0x14
15
rw
TIMx_SMCR
14
Reset value
Reset value
Reset value
Reset value
Reset value
Reset value
rw
Register
TIMx_DIER
TIMx_EGR
TIMx_CR1
TIMx_CR2
TIMx_SR
Bits 15:0 DMAB[15:0]: DMA register for burst accesses
Bits 4:0 DBA[4:0]: DMA base address
TIM1&TIM8 DMA address for full transfer (TIMx_DMAR)
Address offset: 0x4C
Reset value: 0x0000
TIM1&TIM8 register map
TIM1&TIM8 registers are mapped as 16-bit addressable registers as described in the table
below:
TIM1&TIM8 register map and reset values
13
rw
A read or write access to the DMAR register accesses the register located at the address:
“(TIMx_CR1 address) + DBA + (DMA index)” in which:
This 5-bits vector defines the base-address for DMA transfers (when read/write access are
done through the TIMx_DMAR address). DBA is defined as an offset starting from the
address of the TIMx_CR1 register.
Example:
00000: TIMx_CR1,
00001: TIMx_CR2,
00010: TIMx_SMCR,
...
TIMx_CR1 address is the address of the control register 1, DBA is the DMA base address
configured in TIMx_DCR register, DMA index is the offset automatically controlled by the
DMA transfer, depending on the length of the transfer DBL in the TIMx_DCR register.
12
rw
11
rw
10
rw
Reserved
Reserved
Reserved
Reserved
rw
9
Doc ID 13902 Rev 9
Reserved
Reserved
DMAB[15:0]
rw
8
rw
7
rw
6
0
Advanced-control timers (TIM1&TIM8)
0
0
0
rw
ETPS
0
0
0
5
[1:0]
0
0
0
0
0
0
0
0
rw
4
ETF[3:0]
0
0
0
0
0
0
0
0
0
CKD
[1:0]
rw
3
0
0
0
0
0
0
0
0
0
0
MMS[2:0]
CMS
0
0
0
0
0
0
[1:0]
TS[2:0]
rw
2
0
0
0
0
0
0
0
0
0
0
0
0
rw
1
0
0
0
0
0
SMS[2:0]
0
0
0
0
0
0
317/995
0
0
0
0
0
rw
0
0
0
0
0
0
0