MCBSTM32EXL Keil, MCBSTM32EXL Datasheet - Page 429

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MCBSTM32EXL

Manufacturer Part Number
MCBSTM32EXL
Description
BOARD EVALUATION FOR STM32F103ZE
Manufacturer
Keil
Datasheets

Specifications of MCBSTM32EXL

Lead Free Status / RoHS Status
Lead free / RoHS Compliant
RM0008
Mode muxed - asynchronous access muxed NOR Flash
Figure 171. Muxed read accesses
1. The bus turnaround delay (BUSTURN + 1) and the delay between side-by-side transactions overlap, so
Figure 172. Muxed write accesses
The difference with mode D is the drive of the lower address byte(s) on the databus.
BUSTURN  5 has not impact.
AD[15:0]
A[25:16]
NADV
NWE
NOE
AD[15:0]
A[25:16]
NEx
NADV
NWE
NOE
NEx
High
(ADDSET +1)
HCLK cycles
Lower address
Doc ID 13902 Rev 9
(ADDSET +1)
HCLK cycles
Lower address
Memory transaction
(ADDHLD + 1)
HCLK cycles
Memory transaction
ADDHLD
HCLK cycles
1HCLK cycle
(DATAST + 1)
HCLK cycles
Flexible static memory controller (FSMC)
Data sampled
data driven
by memory
data driven by FSMC
(DATAST + 2)
HCLK cycles
2 HCLK
cycles
1HCLK
Data strobe
(BUSTURN + 1)
HCLK cycles
(1)
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