HD6417760BL200AV Renesas Electronics America, HD6417760BL200AV Datasheet - Page 1000

• Manufacturer Part Number: HD6417760BL200AV
• Description: SH4 7760, 17 X17 256BGA, LCDC, U
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417760BL200AV

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: Audio Codec, CAN, EBI/EMI, FIFO, I²C, MFI, MMC, SCI, Serial Sound, SIM, SPI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 69
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

25.3.3
HACCSDR is a 32-bit read/write data register used for accessing the codec register. Write the
command data to HACCSDR. The HAC then transmits the data to the codec via slot 2.
After the codec has responded to a read request (HACRSR.STDRY = 1), the status data received
via slot 2 can be read out from HACCSDR. In both read and write, HACCSAR stores the related
codec register address.
Initial value:
Initial value:
Rev. 2.00 Feb. 12, 2010 Page 916 of 1330
REJ09B0554-0200
Bit
31 to 20 ⎯
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3 to 0
R/W:
R/W:
Bit:
Bit:
Command/Status Data Register (HACCSDR)
Bit Name
CD15/SD15
CD14/SD14
CD13/SD13
CD12/SD12
CD11/SD11
CD10/SD10
CD9/SD9
CD8/SD8
CD7/SD7
CD6/SD6
CD5/SD5
CD4/SD4
CD3/SD3
CD2/SD2
CD1/SD1
CD0/SD0
⎯
CD11/
SD11
R/W
31
15
R
0
0
-
CD10/
SD10
R/W
30
14
-
R
0
0
CD9/
SD9
R/W
29
13
R
0
0
-
Initial Value
All 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
All 0
CD8/
SD8
R/W
28
12
R
0
0
-
CD7/
SD7
R/W
27
11
R
0
0
-
CD6/
R/W
SD6
R/W
R
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
26
10
R
-
0
0
CD5/
SD5
R/W
25
R
-
0
9
0
Description
Reserved
Always 0 for read and write.
Command Data 15 to 0/Status Data 15 to 0
Write data to these bits and then write the codec
register address in HACCSAR. The HAC then
transmits the data to the codec.
Read these bits to get the contents of the codec
register indicated by HACCSAR.
Reserved
Always 0 for read and write.
CD4/
SD4
R/W
24
R
0
8
0
-
CD3/
SD3
R/W
23
R
0
7
0
-
CD2/
SD2
R/W
22
R
0
0
6
-
CD1/
SD1
R/W
21
R
0
5
0
-
CD0/
SD0
R/W
20
R
0
4
0
-
CD15/
SD15
R/W
19
R
0
3
-
0
CD14/
SD14
R/W
18
R
0
2
0
-
CD13/
SD13
R/W
17
R
0
1
-
0
CD12/
SD12
R/W
16
R
0
0
0
-