HD6417760BL200AV Renesas Electronics America, HD6417760BL200AV Datasheet - Page 351

• Manufacturer Part Number: HD6417760BL200AV
• Description: SH4 7760, 17 X17 256BGA, LCDC, U
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417760BL200AV

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: Audio Codec, CAN, EBI/EMI, FIFO, I²C, MFI, MMC, SCI, Serial Sound, SIM, SPI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 69
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

10.5.2
BCR2 is a 16-bit readable/writable register that specifies the bus width for each area and whether
the GPIO interrupt is used.
Do not access off-chip memory space other than area 0 until register initialization is complete.
Initial value:
Note: n = 1 to 6
Bit
15
14
2n + 1
2n
1
0
R/W:
Bit:
Bit
Name
A0SZ1
A0SZ0
AnSZ1
AnSZ0
⎯
STBIRLEN 0
A0SZ1 A0SZ0 A6SZ1 A6SZ0 A5SZ1 A5SZ0 A4SZ1 A4SZ0 A3SZ1 A3SZ0 A2SZ1 A2SZ0 A1SZ1 A1SZ0
Bus Control Register 2 (BCR2)
0/1
15
R
0/1
14
R
Initial
Value
0/1
0/1
All 1
All 1
0
R/W
13
1
R/W
12
1
R/W
R
R
R/W
R/W
⎯
R/W
R/W
11
1
R/W
10
1
Description
Area 0 Bus Width
The off-chip pins (MD4 and MD3) that specify the bus
width are sampled at a power-on reset by the RESET
signal.
00: Setting prohibited
01: 8 bits
10: 16 bits
11: 32 bits
Bus Width Setting
Specifies the bus width of area n.
00: Setting prohibited
01: Bus width is 8 bits
10: Bus width is 16 bits
11: Bus width is 32 bits
Reserved
This bit is always read as 0. The write value should
always be 0.
GPIO Interrupt Enable
0: GPIO interrupt is not used
1: GPIO interrupt is used
R/W
9
1
R/W
8
1
R/W
7
1
Rev. 2.00 Feb. 12, 2010 Page 267 of 1330
R/W
6
1
R/W
5
1
R/W
4
1
R/W
3
1
REJ09B0554-0200
R/W
2
1
1
0
-
-
RLEN
STBI
R/W
0
0