HD6417760BL200AV Renesas Electronics America, HD6417760BL200AV Datasheet - Page 722

SH4 7760, 17 X17 256BGA, LCDC, U

HD6417760BL200AV

Manufacturer Part Number
HD6417760BL200AV
Description
SH4 7760, 17 X17 256BGA, LCDC, U
Manufacturer
Renesas Electronics America
Series
SuperH® SH7750r
Datasheet

Specifications of HD6417760BL200AV

Core Processor
SH-4
Core Size
32-Bit
Speed
200MHz
Connectivity
Audio Codec, CAN, EBI/EMI, FIFO, I²C, MFI, MMC, SCI, Serial Sound, SIM, SPI, USB
Peripherals
DMA, LCD, POR, WDT
Number Of I /o
69
Program Memory Type
ROMless
Ram Size
48K x 8
Voltage - Supply (vcc/vdd)
1.4 V ~ 1.6 V
Data Converters
A/D 4x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
256-BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
HD6417760BL200AV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Part Number:
HD6417760BL200AV
Manufacturer:
RENENAS
Quantity:
20 000
Rev. 2.00 Feb. 12, 2010 Page 638 of 1330
REJ09B0554-0200
Bit
5
4
Bit
Name
ORER
ERS
Initial
Value
0
0
R/W
R/W
R/W
Description
Overrun Error
Indicates that an overrun error resulting in abnormal
termination has occurred during reception..
0: Indicates that reception is in progress, or that reception
[Clearing Conditions]
1: Indicates that an overrun error occurred during reception*
[Setting Condition]*
Notes: 1. Clearing the RE bit in SISCR to 0 will retain the
Error Signal Status
This flag indicates the status of error signals returned from
the receiver during transmission. In the T = 1 mode, this bit is
not set.
0: Indicates that an error signal indicating detection of a
[Clearing Conditions]
1: Indicates that an error signal indicating detection of a
[Setting Condition]
Note: Clearing the TE bit in SISCR to 0 will retain the
parity error was not sent from the receiver.
parity error was sent from the receiver.
was completed normally*
On reset
When 0 is written to ORER
When the next serial reception is completed in the RDRF
= 1 state.
On reset
When 0 is written to ERS
When an error signal is sampled.
2. SIRDR loses the data received before the overrun
3. Writing 1 will retain the original value.
previous state without affecting the ERS flag.
previous state without affecting the ORER flag.
error but retains the data received at the time the
overrun error occurred. Furthermore, if ORER is
set to 1, then subsequent serial reception cannot
continue.
3
1
2

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