HD6417760BL200AV Renesas Electronics America, HD6417760BL200AV Datasheet - Page 461

• Manufacturer Part Number: HD6417760BL200AV
• Description: SH4 7760, 17 X17 256BGA, LCDC, U
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417760BL200AV

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: Audio Codec, CAN, EBI/EMI, FIFO, I²C, MFI, MMC, SCI, Serial Sound, SIM, SPI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 69
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

10.6.11 Bus Release and Acquire Sequences
This LSI controls the bus unless it receives a bus request.
As soon as an assertion (low level) of the bus request signal (BREQ) is received from an off-chip
device and the current bus cycle being executed ends, this LSI releases the bus and asserts (low
level) the bus request acknowledge signal (BACK). If a bus request has not been issued due to a
refresh request, this LSI receives the BREQ negation (high level) indicating that the slave has
released the bus, and then negates (drives high) the BACK signal and resumes use of the bus.
If a bus request is issued due to a refresh request in the bus release state, this LSI negates the bus
request acknowledge signal (BACK) and then receives the BREQ negation indicating that the
slave has released the bus, and resumes use of the bus.
When the bus is released, all bus control output signals and input/output signals pertaining to the
bus interface go to the high-impedance state except for CKE in the synchronous DRAM interface,
BACK (bus request acknowledge) in bus arbitration, and DACK0 and DACK1 for DMA transfer
control.
For synchronous DRAM, a precharge command is issued for the active bank, and the bus is
released after precharging is completed.
The following is the specific bus release sequence.
First, the bus request acknowledge signal is asserted at the rising edge of the clock. The address
bus and data bus go to the high-impedance state in synchronization with the assertion of BACK.
At the same time, the bus control signals (BS, CSn, RAS, WEn, RD, RD/WR, CE2A, and CE2B)
CKIO
BREQ
BACK
A25−A0
CSn
RD/WR
RD
WEn
D31−D0
Must be asserted for at least 2 cycles
HiZ
Figure 10.61 Arbitration Sequence
HiZ
HiZ
HiZ
HiZ
HiZ
HiZ
Must be negated within 2 cycles
Rev. 2.00 Feb. 12, 2010 Page 377 of 1330
REJ09B0554-0200