HD6417760BL200AV Renesas Electronics America, HD6417760BL200AV Datasheet - Page 911

• Manufacturer Part Number: HD6417760BL200AV
• Description: SH4 7760, 17 X17 256BGA, LCDC, U
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417760BL200AV

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: Audio Codec, CAN, EBI/EMI, FIFO, I²C, MFI, MMC, SCI, Serial Sound, SIM, SPI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 69
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

22.5.8
The CANTXCR are two 16-bit read/conditionally-write registers. The CANTXCR1 controls
Mailbox 31 to Mailbox 16, and the CANTXCR0 controls Mailbox 15 to Mailbox 1. These
registers are used by the microprocessor to request the pending transmission requests in the
CANTXPR to be cancelled. To clear the corresponding bit in CANTXPR, the host CPU must
write a 1 to the corresponding CANTXCR bit. Writing a 0 has no effect.
When an abort has succeeded, the CAN controller clears the corresponding CANTXPR and
CANTXCR bits, and sets the corresponding CANABACK bit. However, once a Mailbox has
started transmission, the transmission cannot be canceled by this bit. In such case, if the
transmission is finishes in success, the CAN controller clears the corresponding CANTXPR and
CANTXCR bits, and sets the corresponding CANTXACK bit, however, if the transmission fails
due to a bus arbitration loss or an error on the bus, the CAN controller clears the corresponding
CANTXPR and CANTXCR bits, and sets the corresponding CANABACK bit. If an attempt is
made by the host CPU to clear Mailbox transmission that is not transmit-pending, it shall have no
effect, and will be automatically cleared when an internal arbitration for transmission runs.
• CANTXCR1
Initial value:
Note:
Bit
15 to 0
R/W:
Bit:
* A write of 1 only is allowed for the Mailbox designated for transmission when it is in the
Transmit Cancel Registers 1 and 0 (CANTXCR1, CANTXCR0)
TXCR1
Bit Name
TXCR1[15:0]
R/W*
_15
wait state.
15
0
TXCR1
R/W*
_14
14
0
TXCR1
R/W*
_13
13
0
Initial Value
All 0
TXCR1
R/W*
_12
12
0
TXCR1
R/W*
_11
11
0
TXCR1
R/W*
_10
10
0
R/W
R/W*
TXCR1
R/W*
_9
9
0
TXCR1
R/W*
_8
8
0
Description
Requests the corresponding Mailbox that is in
the queue for transmission, to cancel its
transmission. Bits 15 to 0 correspond to
Mailboxes 31 to 16 (and TXPR1[15:0])
respectively.
0: Transmit message cancellation idle state in
1: Transmission cancellation request made
corresponding mailbox.
Clearing condition: Completion of transmit
message cancellation (automatically cleared)
for the corresponding Mailbox.
TXCR1
R/W*
_7
0
7
TXCR1
Rev. 2.00 Feb. 12, 2010 Page 827 of 1330
R/W*
_6
6
0
TXCR1
R/W*
_5
5
0
TXCR1
R/W*
_4
4
0
TXCR1
R/W*
_3
3
0
REJ09B0554-0200
TXCR1
R/W*
_2
2
0
TXCR1
R/W*
_1
1
0
TXCR1
R/W*
_0
0
0