HD6417760BL200AV Renesas Electronics America, HD6417760BL200AV Datasheet - Page 501

SH4 7760, 17 X17 256BGA, LCDC, U

HD6417760BL200AV

Manufacturer Part Number
HD6417760BL200AV
Description
SH4 7760, 17 X17 256BGA, LCDC, U
Manufacturer
Renesas Electronics America
Series
SuperH® SH7750r
Datasheet

Specifications of HD6417760BL200AV

Core Processor
SH-4
Core Size
32-Bit
Speed
200MHz
Connectivity
Audio Codec, CAN, EBI/EMI, FIFO, I²C, MFI, MMC, SCI, Serial Sound, SIM, SPI, USB
Peripherals
DMA, LCD, POR, WDT
Number Of I /o
69
Program Memory Type
ROMless
Ram Size
48K x 8
Voltage - Supply (vcc/vdd)
1.4 V ~ 1.6 V
Data Converters
A/D 4x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
256-BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-

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Company
Part Number
Manufacturer
Quantity
Price
Part Number:
HD6417760BL200AV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Part Number:
HD6417760BL200AV
Manufacturer:
RENENAS
Quantity:
20 000
Bit
17
16
15 to 10 ⎯
9
8
7 to 3
Bit Name
RDS
RDE
TAM1
TAM0
Initial Value
0
0
All 0
0
0
All 0
R/W
R/W
R/W
R
R/W
R/W
R
Description
HAC/SSI Receive DMA Termination
Setting this bit to 1 forcibly terminates the receive
DMA transfer.
0: Write operation is ignored
1: Receive DMA transfer is forcibly terminated
0: Transfer is completed
1: Transfer is being performed
HAC/SSI Receive DMA Transfer Activation
Control
Controls the receive DMA transfer activation. Write
operation is ignored during transfer. To reactivate
a receive DMA transfer, read this bit as 0 and then
write 1 to it.
0: Write operation is ignored
1: Receive DMA transfer is activated
0: Transfer is completed
1: Transfer is being performed
Reserved
These bits are always read as 0. The write value
should always be 0.
Transmit Data Alignment Setting
These bits specify the data alignment method for
reading transmit data from an external memory.
For details of the data alignment method for the
transmit slot data and external bus, see Table 11.5
(2).
00: Alignment control is not performed
01: A longword is transferred as four bytes
10: A longword is transferred as two words
11: Setting prohibited
Reserved
These bits are always read as 0. The write value
should always be 0.
When writing
When reading
When writing
When reading
Rev. 2.00 Feb. 12, 2010 Page 417 of 1330
REJ09B0554-0200

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