HD6417760BL200AV Renesas Electronics America, HD6417760BL200AV Datasheet - Page 1174

• Manufacturer Part Number: HD6417760BL200AV
• Description: SH4 7760, 17 X17 256BGA, LCDC, U
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417760BL200AV

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: Audio Codec, CAN, EBI/EMI, FIFO, I²C, MFI, MMC, SCI, Serial Sound, SIM, SPI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 69
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

30.3.19 LCDC Control Register (LDCNTR)
LDCNTR specifies start and stop of display by the LCDC.
The LCDC begins display when a value of 1 is input to both the DON2 bit and the DON bit.
Power is then supplied to the LCD module in accordance with the sequence set by the LDPMM
and LDCNTR. The sequence ends when the LPS[1:0] value changes from B'00 to B'11. Do not
make any action to the DON bit until the sequence ends.
The LCDC stops display when a value of 0 is input to the DON bit. Power to the LCD module is
cut off in accordance with the sequence set by the LDPMMR and LDCNTR. The sequence ends
when the LPS[1:0] value changes from B'11 to B'00. Do not make any action to the DON bit until
the sequence ends.
Initial value:
Rev. 2.00 Feb. 12, 2010 Page 1090 of 1330
REJ09B0554-0200
Bit
7
6
5
4
3
2
1
0
R/W:
Bit:
Bit Name
OFFE3
OFFE2
OFFE1
OFFE0
OFFF3
OFFF2
OFFF1
OFFF0
15
R
0
-
14
R
0
-
13
R
0
-
Initial Value
0
0
0
0
1
1
1
1
12
R
0
-
11
R
0
-
10
R
0
-
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
9
0
-
Description
LCDC Power-Off Sequence Period
Sets the period from VEPWC negation to stopping
output of the display data (LCD_DATA) and timing
signals (LCD_FLM, LCD_CL1, LCD_CL2, and
LCD_M_DISP) in the power-off sequence of the
LCD module in frame units.
Specify a value of (the period) −1.
This period is the (e) period in figures 30.4 to 30.7,
Power-Supply Control Sequence and States of the
LCD Module.
LCDC Power-Off Sequence Period
Sets the period from stopping output of the display
data (LCD_DATA) and timing signals (LCD_FLM,
LCD_CL1, LCD_CL2, and LCD_M_DISP) to
VCPWC negation in the power-off sequence of the
LCD module in frame units.
Specify a value of (the period) −1.
This period is the (f) period in figures 30.4 to 30.7,
Power-Supply Control Sequence and States of the
LCD Module.
R
8
0
-
7
0
R
-
0
R
6
-
R
5
0
-
DON2
R/W
4
0
3
0
R
-
2
0
R
-
R
1
0
-
DON
R/W
0
0