HD6417760BL200AV Renesas Electronics America, HD6417760BL200AV Datasheet - Page 1219

• Manufacturer Part Number: HD6417760BL200AV
• Description: SH4 7760, 17 X17 256BGA, LCDC, U
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417760BL200AV

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: Audio Codec, CAN, EBI/EMI, FIFO, I²C, MFI, MMC, SCI, Serial Sound, SIM, SPI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 69
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

3. With a post-execution break, the instruction set as a break condition is executed, then a break
4. When an instruction access cycle is set for channel B, BDRB is ignored in determining
31.3.5
1. In the case of an operand access cycle break, the bits included in address bus comparison vary
2. When a data value is included in break conditions in channel B
3.
interrupt is generated before the next instruction is executed. When a post-execution break is
set for a delayed branch instruction, the delay slot is executed and the break is effected before
execution of the instruction at the branch destination (when the branch is made) or the
instruction two instructions ahead of the branch instruction (when the branch is not made).
whether there is an instruction access match. Therefore, a break condition specified by the
DBEB bit in BRCR is not executed.
as shown below according to the data size specification in BBRA and BBRB.
When a data value is included in the break conditions, set the DBEB bit in BRCR to 1. In this
case, BDRB and BDMRB settings are necessary in addition to the address condition. A user
break interrupt is generated when all three conditions, address, ASID, and data, are matched.
When a quadword access occurs, the 64-bit access data is divided into an upper 32 bits and
lower 32 bits, and interpreted as two 32-bit data units. A break is generated if either of the 32-
bit data units satisfies the data match condition.
Set the IDB1 to IDB0 bits in BBRB to B'10 or B'11. When byte data is specified, the same data
should be set to bits 15 to 8 and bits 7 to 0 in BDRB and BDMRB. When word or byte is set,
bits 31 to 16 in BDRB and BDMRB are ignored.
Data Size
Quadword
Longword
Word
Byte
Not included in condition
When the DBEB bit in BRCR is set to 1, a break is not generated by an operand access with
no access data (an operand access in a PREF, OCBP, OCBWB, or OCBI instruction).
Operand Access Cycle Break
Address Bits Compared
Address bits A31 to A3
Address bits A31 to A2
Address bits A31 to A1
Address bits A31 to A0
In quadword access, address bits A31 to A3
In longword access, address bits A31 to A2
In word access, address bits A31 to A1
In byte access, address bits A31 to A0
Rev. 2.00 Feb. 12, 2010 Page 1135 of 1330
REJ09B0554-0200