HD6417760BL200AV Renesas Electronics America, HD6417760BL200AV Datasheet - Page 126

• Manufacturer Part Number: HD6417760BL200AV
• Description: SH4 7760, 17 X17 256BGA, LCDC, U
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417760BL200AV

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: Audio Codec, CAN, EBI/EMI, FIFO, I²C, MFI, MMC, SCI, Serial Sound, SIM, SPI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 69
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Rev. 2.00 Feb. 12, 2010 Page 42 of 1330
REJ09B0554-0200
31
Notes: 1.
(a) Register configuration
in user mode
Figure 2.2 CPU Register Configuration in Each Processing Mode
2.
3.
4.
R0 _ BANK0*
R1 _ BANK0*
R2 _ BANK0*
R3 _ BANK0*
R4 _ BANK0*
R5 _ BANK0*
R6 _ BANK0*
R7 _ BANK0*
R0 is used as the index register in indexed register-indirect addressing mode and
indexed GBR indirect addressing mode.
Banked registers
Banked registers
Accessed as general registers when the RB bit is set to 1 in SR. Accessed only by
LDC/STC instructions when the RB bit is cleared to 0.
Banked registers
Accessed as general registers when the RB bit is cleared to 0 in SR. Accessed only
by LDC/STC instructions when the RB bit is set to 1.
MACH
MACL
GBR
R10
R11
R12
R13
R14
R15
SR
PR
PC
R8
R9
1,
*
2
2
2
2
2
2
2
2
0
31
(b) Register configuration in
privileged mode (RB = 1)
R0 _ BANK1*
R0 _ BANK0*
R1 _ BANK1*
R2 _ BANK1*
R3 _ BANK1*
R4 _ BANK1*
R5 _ BANK1*
R6 _ BANK1*
R7 _ BANK1*
R1 _ BANK0*
R2 _ BANK0*
R3 _ BANK0*
R4 _ BANK0*
R5 _ BANK0*
R6 _ BANK0*
R7 _ BANK0*
MACH
MACL
SSR
GBR
VBR
SPC
SGR
DBR
R10
R11
R12
R13
R14
R15
PR
SR
PC
R8
R9
1,
1,
3
3
3
3
3
3
3
4
4
4
4
4
4
4
*
*
3
4
0
31
(c) Register configuration in
privileged mode (RB = 0)
R0 _ BANK0*
R0 _ BANK1*
R1 _ BANK0*
R2 _ BANK0*
R3 _ BANK0*
R4 _ BANK0*
R5 _ BANK0*
R6 _ BANK0*
R7 _ BANK0*
R1 _ BANK1*
R2 _ BANK1*
R3 _ BANK1*
R4 _ BANK1*
R5 _ BANK1*
R6 _ BANK1*
R7 _ BANK1*
MACH
MACL
GBR
SGR
SSR
VBR
SPC
DBR
R10
R11
R12
R13
R14
R15
PR
SR
PC
R8
R9
1,
1,
*
4
4
4
4
4
4
4
*
3
3
3
3
3
3
3
4
3
0