HD6417760BL200AV Renesas Electronics America, HD6417760BL200AV Datasheet - Page 520

• Manufacturer Part Number: HD6417760BL200AV
• Description: SH4 7760, 17 X17 256BGA, LCDC, U
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417760BL200AV

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: Audio Codec, CAN, EBI/EMI, FIFO, I²C, MFI, MMC, SCI, Serial Sound, SIM, SPI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 69
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

• Burst Mode
Rev. 2.00 Feb. 12, 2010 Page 436 of 1330
REJ09B0554-0200
In burst mode, once the DMAC has acquired the bus it holds the bus and transfers data
continuously until the transfer end condition is satisfied. With DREQ low level detection in
external request mode, however, when DREQ is driven high the bus passes to another bus
master after the end of the DMAC transfer request that has already been accepted, even if the
transfer end condition has not been satisfied.
Figure 11.11 shows an example of DMA transfer timing in burst mode. The following transfer
conditions are used in this example:
⎯ Single address mode
⎯ DREQ level detection (DS = 0 and TM = 1 in CHCRn, external request 2-channel mode)
Note:
Bus cycle
Bus cycle
DREQ
DREQ
Specify DREQ edge detection when performing burst transfer in DMABRG mode.
Operations in burst mode with DREQ level detection in DMABRG mode are the
same as those in cycle steal mode.
Figure 11.10 Example of DMA Transfer in Cycle Steal Mode
Figure 11.11 Example of DMA Transfer in Burst Mode
CPU
CPU
CPU
CPU
CPU
CPU
DMAC
DMAC
Read
DMAC
DMAC
Write
Bus returned to CPU
DMAC
CPU
DMAC
DMAC
Read
DMAC
DMAC
Write
DMAC
CPU
CPU
CPU