HD6417760BL200AV Renesas Electronics America, HD6417760BL200AV Datasheet - Page 144

• Manufacturer Part Number: HD6417760BL200AV
• Description: SH4 7760, 17 X17 256BGA, LCDC, U
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417760BL200AV

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: Audio Codec, CAN, EBI/EMI, FIFO, I²C, MFI, MMC, SCI, Serial Sound, SIM, SPI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 69
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

The FPU exception cause field in FPSCR contains bits corresponding to all of above sources E, V,
Z, O, U, and I, and the FPU exception flag and enable fields in FPSCR contain bits corresponding
to sources V, Z, O, U, and I, but not E. Thus, FPU errors cannot be disabled.
When an FPU exception occurs, the corresponding bit in the FPU exception cause field is set to 1,
and 1 is added to the corresponding bit in the FPU exception flag field. When an FPU exception
does not occur, the corresponding bit in the FPU exception cause field is cleared to 0, but the
corresponding bit in the FPU exception flag field remains unchanged.
3.5.3
FPU exception handling is initiated in the following cases:
• FPU error (E): FPSCR.DN = 0 and a denormalized number is input
• Invalid operation (V): FPSCR.Enable.V = 1 and (instruction = FTRV or invalid operation)
• Division by zero (Z): FPSCR.Enable.Z = 1 and division with a zero divisor
• Overflow (O): FPSCR.Enable.O = 1 and instruction with possibility of operation result
• Underflow (U): FPSCR.Enable.U = 1 and instruction with possibility of operation result
• Inexact exception (I): FPSCR.Enable.I = 1 and instruction with possibility of inexact operation
These possibilities are shown in the individual instruction descriptions. All exception events that
originate in the FPU are assigned as the same exception event. The meaning of an exception is
determined by software by reading from FPSCR and interpreting the information it contains. If no
bits are set in the FPU exception cause field of FPSCR when one or more of bits O, U, I, and V (in
case of FTRV only) are set in the FPU exception enable field, this indicates that an actual
exception source is not generated. Also, the destination register is not changed by any FPU
exception handling operation.
Except for the above, the FPU disables exception handling. In every processing, the bit
corresponding to source V, Z, O, U, or I is set to 1, and a default value is generated as the
operation result.
• Invalid operation (V): qNaN is generated as the result.
• Division by zero (Z): Infinity with the same sign as the unrounded value is generated.
• Overflow (O):
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REJ09B0554-0200
overflow
underflow
result
When rounding mode = RZ, the maximum normalized number, with the same sign as the
unrounded value, is generated.
When rounding mode = RN, infinity with the same sign as the unrounded value is generated.
FPU Exception Handling