HD6417760BL200AV Renesas Electronics America, HD6417760BL200AV Datasheet - Page 1126

• Manufacturer Part Number: HD6417760BL200AV
• Description: SH4 7760, 17 X17 256BGA, LCDC, U
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417760BL200AV

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: Audio Codec, CAN, EBI/EMI, FIFO, I²C, MFI, MMC, SCI, Serial Sound, SIM, SPI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 69
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Register Name
A/D conversion data register A
A/D conversion data register B
A/D conversion data register C
A/D conversion data register D
A/D conversion control/status register ADCSR
A/D conversion data register A
A/D conversion data register B
A/D conversion data register C
A/D conversion data register D
A/D conversion control/status register ADCSR
29.3
The A/D converter has the following registers. For details of register addresses and register states
during each process, see section 32, List of Register.
Table 29.2 Register Configuration (1)
Table 29.2 Register Configuration (2)
Register Name
Notes: 1. Before entering module standby or software standby mode, check that A/D conversion
Rev. 2.00 Feb. 12, 2010 Page 1042 of 1330
REJ09B0554-0200
2. Only 0 can be written to bit 15 for clearing the flag.
3. After exiting hardware standby mode, this LSI enters the power-on reset state by the
Register Descriptions
is not in progress. If standby mode is entered while A/D conversion is in progress,
correct register values are not guaranteed.
RESET pin.
Abbrev.
ADDRA
ADDRB
ADDRC
ADDRD
ADDRA
ADDRB
ADDRC
ADDRD
Abbrev.
R/W
R
R
R
R
R/W*
H'0000
H'0000
H'0000
H'0000
H'0040
Power-on
Reset by
RESET
Pin/WDT/
H-UDI
2
P4 Address
H'FE28 0000
H'FE28 0002
H'FE28 0004
H'FE28 0006
H'FE28 0008
Manual Reset
by RESET
Pin/WDT/
Multiple
Exception
H'0000
H'0000
H'0000
H'0000
H'0040
Area 7 Address Size
H'1E28 0000
H'1E28 0002
H'1E28 0004
H'1E28 0006
H'1E28 0008
Retained
Retained
Retained
Retained
Retained
Sleep
by Sleep
Instruction/
Deep Sleep
by
Hardware
16
16
16
16
16
*
3
Standby
H'0000*
H'0040*
by
Software/
Each
Module
H'0000*
H'0000*
H'0000*
Sync
Clock
Pck
Pck
Pck
Pck
Pck
1
1
1
1
1