HD6417760BL200AV Renesas Electronics America, HD6417760BL200AV Datasheet - Page 479

• Manufacturer Part Number: HD6417760BL200AV
• Description: SH4 7760, 17 X17 256BGA, LCDC, U
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417760BL200AV

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: Audio Codec, CAN, EBI/EMI, FIFO, I²C, MFI, MMC, SCI, Serial Sound, SIM, SPI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 69
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Bit
13
12
11
10
9
8
7
6
5
4
Bit Name
SM1
SM0
RS3
RS2
RS1
RS0
TM
TS2
TS1
TS0
Initial Value
0
0
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Description
Source Address Mode 1 and 0
These bits specify incrementing/decrementing of
the DMA transfer source address. The
specification of these bits is ignored when data is
transferred from an external device to external
memory in single address mode.
00: Source address fixed
01: Source address incremented (+1 in 8-bit
10: Source address decremented (–1 in 8-bit
11: Setting prohibited
Resource Select 3 to 0
These bits specify the transfer request source.
Setting bits DMS1 and DMS0 in DMAOR specifies
the transfer request source in external request 2-
channel mode or DMABRG mode.
See tables 11.3 and 11.4 for settings of bits RS3
to RS0.
Transmit Mode
Specifies the bus mode for transfer.
0: Cycle steal mode
1: Burst mode
Transmit Size 2 to 0
These bits specify the transfer data size (access
size).
000: Quadword size (64-bit) specification
001: Byte size (8-bit) specification
010: Word size (16-bit) specification
011: Longword size (32-bit) specification
100: 32-byte block transfer specification
Other than above: Setting prohibited
transfer, +2 in 16-bit transfer, +4 in 32-bit
transfer, +8 in 64-bit transfer, +32 in 32-byte
burst transfer)
transfer, –2 in 16-bit transfer, –4 in 32-bit
transfer, –8 in 64-bit transfer, –32 in 32-byte
burst transfer)
Rev. 2.00 Feb. 12, 2010 Page 395 of 1330
REJ09B0554-0200