HD6417760BL200AV Renesas Electronics America, HD6417760BL200AV Datasheet - Page 558

• Manufacturer Part Number: HD6417760BL200AV
• Description: SH4 7760, 17 X17 256BGA, LCDC, U
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417760BL200AV

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: Audio Codec, CAN, EBI/EMI, FIFO, I²C, MFI, MMC, SCI, Serial Sound, SIM, SPI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 69
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Rev. 2.00 Feb. 12, 2010 Page 474 of 1330
REJ09B0554-0200
Figure 11.34 Forced Termination and Resume Procedures for DMA Audio Transfer
Disable interrupt for corresponding transfer
[2] Set termination bit in DMAACR
[1] Stop HAC or SSI DMA transfer
DMAACR.TDS = 1 (transmitting)
DMAACR.RDS = 1 (receiving)
TDS == 0? (transmitting)
Forced termination and
RDS == 0? (receiving)
resume procedure
(if necessary)
Transfer end
resuming?
Is transfer
Yes
No
No
Yes
1.
2.
Reactivating the related DMA
To forcibly terminate DMA transfer in HAC or SSI before the specified bytes are
transferred, disable DMA in HAC or SSI that are being used.
With transfer terminate interrupt enabled, it is generated when the terminated
DMA stops completely.
When the DMA stop causes overrun or underrun in HAC or SSI,
the related interrupt should be generated.
To avoid interrupt generation, disable the related interrupts beforehand.
Setting the forced termination bit in DMAACR stops DMA in HAC or SSI.
However, it is only after the completion of the bus cycle being performed that
DMA stops completely.
Activating DMA before it completely stops will not take effect.
To know whether DMA has completely stopped, read the forced termination bit
in DMAACR. When the read value is 1, DMA has not stopped. Make sure that
the forced termination bit in DMAACR is 0 before activating DMA again.
In the receive operation, all received data may not be stored in synchronous
DRAM at the DMA forced termination since received data is temporarily stored
in FIFO first. Therefore, the forced termination bit in DMAACR will be cleared
to 0 when all received data is completely stored in synchronous DRAM.
DMAACR.RDE = 1 (receiving)
DMAACR.TDE = 1 (transmitting)
Set transfer address and number of bytes
Set HAC or SSI DMA again
-When HAC is in use:
-When SSI is in use:
to calculate number of transfers remained
Enable interrupt for corresponding transfer
When HAC is in use:
When SSI is in use:
DMAARXDAR/DMAARXTCR (receiving)
DMAATXSAR/DMAATXTCR (transmitting)
Read DMAARXTCNT when receiving or
HACACR.*DMA*_EN = 1
SSICR.DMEN = 1
DMAATXTCNT when trasmitting
Transfer resume
(if necessary)
HACACR.*DMA*_EN = 0
SSICR.EN = 0