HD6417760BL200AV Renesas Electronics America, HD6417760BL200AV Datasheet - Page 303

• Manufacturer Part Number: HD6417760BL200AV
• Description: SH4 7760, 17 X17 256BGA, LCDC, U
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417760BL200AV

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: Audio Codec, CAN, EBI/EMI, FIFO, I²C, MFI, MMC, SCI, Serial Sound, SIM, SPI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 69
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

8.6
1. Return from exception handling
2. If an exception or interrupt occurs when BL bit in SR = 1
3. SPC when an exception occurs
4.
If the delay slot instruction has a second data transfer, two checks are performed in step 2, as in
the above case (Instructions that make two accesses to memory).
If the accepted exception (the highest-priority exception) is a delay slot instruction re-
execution type exception, the branch instruction PR register write operation (PC → PR
operation performed in a BSR, BSRF, or JSR instruction) is not disabled.
A. Check the BL bit in SR with software. If SPC and SSR have been saved to external
B. Issue an RTE instruction. When RTE is executed, the SPC contents are saved in PC, the
A. Exception
B. Interrupt
A. Re-execution type exception
B. Completion type exception or interrupt
An exception must not be generated in an RTE instruction delay slot, as the operation cannot
be guaranteed in this case.
memory, set the BL bit in SR to 1 before restoring them.
SSR contents are saved in SR, and branch is made to the SPC address to return from the
exception handling routine.
When an exception other than a user break occurs, a manual reset is executed. The value in
EXPEVT at this time is H'0000 0020; the SPC and SSR contents are undefined.
The PC value for the instruction at which the exception occurred is set in SPC, and the
instruction is re-executed after returning from the exception handling routine. If an
exception occurs in a delay slot instruction, however, the PC value for the delay slot
instruction is saved in SPC regardless of whether or not the preceding delay slot instruction
condition is satisfied.
If an ordinary interrupt occurs, the interrupt request is held pending and is accepted after
the BL bit in SR has been cleared to 0 by software. If a nonmaskable interrupt (NMI)
occurs, it can be held pending or accepted according to the setting made by software.
In sleep or standby mode, however, an interrupt is accepted even if the BL bit in SR is set
to 1.
The PC value for the instruction following that at which the exception occurred is set in
SPC. If an exception occurs in a branch instruction with delay slot, however, the PC value
for the branch destination is saved in SPC.
Usage Notes
Rev. 2.00 Feb. 12, 2010 Page 219 of 1330
REJ09B0554-0200