HD6417760BL200AV Renesas Electronics America, HD6417760BL200AV Datasheet - Page 1035

• Manufacturer Part Number: HD6417760BL200AV
• Description: SH4 7760, 17 X17 256BGA, LCDC, U
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417760BL200AV

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: Audio Codec, CAN, EBI/EMI, FIFO, I²C, MFI, MMC, SCI, Serial Sound, SIM, SPI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 69
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Some states of the multimedia card cause command sequence on the multimedia card side to stop.
Table 26.6 shows the card states in which a command sequence is halted. In this case, the
command sequence should also be aborted by setting the CMDOFF bit to 1 on the MMCIF side.
Table 26.6 Card States in which Command Sequence is Halted
In write data transmission, the contents of the command response and data response should be
analyzed, and then transmission should be triggered. In addition, the transfer clock (MCCLK)
output should be temporarily halted by FIFO full/empty, and it should be resumed when the
preparation has been completed.
Bit
4
3 to 0
Card Operating Mode
MMC mode
Bit
Name
DATAEN
—
Command response
Data status
Initial
Value
0
All 0
R/W
R/W
R
Error Status
When the error detection bit in the card status (32 bits)
in the command response data transmitted by the card
is set.
When the CRCERI bit is set due to an error in the CRC
status to be transmitted from the card is set while block
data is transmitted to the card.
Description
Data Enable
Starts write data transmission by a command with
write data. This bit is cleared automatically when 1 is
written. Resumes transfer clock output and write data
transmission when the transfer clock has been halted
by FIFO empty or termination of one block writing in
multiblock write.
Write enabled period: (1) after receiving a response to
a command with write data, (2) while transfer clock is
halted by FIFO empty, (3) when one block writing in
multiblock write is terminated
Write of 0: Operation is not affected.
Write of 1: Starts or resumes transfer clock output
Reserved
These bits are always read as 0. The write value
should always be 0.
and write data transmission.
Rev. 2.00 Feb. 12, 2010 Page 951 of 1330
REJ09B0554-0200