HD6417760BL200AV Renesas Electronics America, HD6417760BL200AV Datasheet - Page 1160

• Manufacturer Part Number: HD6417760BL200AV
• Description: SH4 7760, 17 X17 256BGA, LCDC, U
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417760BL200AV

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: Audio Codec, CAN, EBI/EMI, FIFO, I²C, MFI, MMC, SCI, Serial Sound, SIM, SPI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 69
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

30.3.6
When a DSTN panel is used, LDSARL specifies the fetch start address for the lower side of the
panel.
Initial value:
Initial value:
Rev. 2.00 Feb. 12, 2010 Page 1076 of 1330
REJ09B0554-0200
Bit
31 to 28 ⎯
27, 26
25 to 0
R/W:
R/W:
Bit:
Bit:
3.
LCDC Display Start Address Register – Lower (LDSARL)
SAL15 SAL14 SAL13 SAL12 SAL11 SAL10
Bit Name Initial Value
⎯
SAL25
to
SAL0
R/W
31
15
R
0
0
-
The minimum alignment unit of LDSARU and LDSARL is four bytes. Because the
LCDC handles these values as longword data, the values written to the lower two bits
of each register are always treated as 0. The lower two bits of each register are always
read as 0. For 1 or 2 bpp, set the registers so that the start of each line is aligned with
the longword boundary (32 bits). (Data at the start of each line is always valid.) Data
that exceeds the longword boundary at the end of each line (1, 2, or 3 bytes) will be
discarded. For 4, 8, 15, or 16 bpp, set the registers so that the start of each line is
aligned with the longword boundary (32 bits).
R/W
30
14
-
R
0
0
All 0
All 1
All 0
R/W
29
13
R
0
0
-
R/W
28
12
R
0
0
-
R/W
27
11
R
1
0
-
R
R
R/W
R/W
R/W
26
10
R
-
1
0
SAL25 SAL24 SAL23 SAL22 SAL21 SAL20 SAL19 SAL18 SAL17 SAL16
SAL9
Description
Reserved
These bits are always read as 0. The write value
should always be 0.
Reserved
These bits are always read as 1. The write value
should always be 1.
Start Address for Lower Panel Display Data Fetch
The start address for data fetch of the display data
must be set within the synchronous DRAM area of
area 3.
STN and TFT: Cannot be used
DSTN: Start address for fetching display data
corresponding to the lower panel
R/W
R/W
25
0
9
0
SAL8
R/W
R/W
24
0
8
0
SAL7
R/W
R/W
23
0
7
0
SAL6
R/W
R/W
22
0
0
6
SAL5
R/W
R/W
21
0
5
0
SAL4
R/W
R/W
20
0
4
0
SAL3
R/W
R/W
19
0
3
0
SAL2
R/W
R/W
18
0
2
0
SAL1
R/W
R/W
17
0
1
0
SAL0
R/W
R/W
16
0
0
0