HD6417760BL200AV Renesas Electronics America, HD6417760BL200AV Datasheet - Page 569

• Manufacturer Part Number: HD6417760BL200AV
• Description: SH4 7760, 17 X17 256BGA, LCDC, U
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417760BL200AV

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: Audio Codec, CAN, EBI/EMI, FIFO, I²C, MFI, MMC, SCI, Serial Sound, SIM, SPI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 69
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

• When data transfer of half of the bytes specified in DMAARXTCR is completed on the
• When data transfer of half of the bytes specified in DMAARXTCR is completed on the receive
• When data transfer of half of the bytes specified in DMAARXTCR is completed on the
The DMABRG outputs three types of interrupt requests to the INTC: an all data transfer end
interrupt, a half data transfer end interrupt and an address error interrupt. To know which interrupt
the DMABRG has issued, read interrupt flag bits in DMABRGCR. An interrupt flag bit that is set
to 1 indicates the corresponding interrupt has been output.
11.7
1. When modifying SAR, DAR, DMATCR, and CHCR, first clear the DE bit for the relevant
2. Inputting an NMI interrupt with the DMAC not operating sets the NMIF bit in DMAOR.
3. Check that DMA transfer is not in progress before making a transition to module standby state,
4. Do not specify a DMAC, cache, BSC, or UBC control register as the DMAC transfer source or
transmit side for channel 1 of the HAC or SSI with the A1TXHE bit in DMABRGCR set to 1,
the A1TXHF bit in DMABRGCR is set to 1 and an interrupt request is output to the INTC.
side for channel 0 of the HAC or SSI with the A0RXHE bit in DMABRGCR set to 1, the
DMABRG sets the A0RXHF bit in DMABRGCR to 1 and outputs an interrupt request to the
INTC.
transmit side for channel 0 of the HAC or SSI with the A0TXHE bit in DMABRGCR set to 1,
the DMABRG sets the A0TXHF bit in DMABRGCR to 1 and outputs an interrupt request to
the INTC.
channel.
⎯ When DMA transfer is not correctly performed, take the following actions:
standby mode, or deep sleep mode.
Either check CHCR.TE = 1, or set DMAOR.DME = 0 to terminate DMA transfer. Setting
DMAOR.DME = 0 stops the transfer on the completion of the DMA bus cycle currently being
performed. Note, therefore, that transfer may not end immediately, depending on the transfer
data size. DMA operation is not guaranteed if module standby state, standby mode, or deep
sleep mode is entered without confirming that DMA transfer has ended.
destination.
Read the NMIF, AE, and DME bits in DMAOR, the DE and TE bits in CHCR, and
DMATCR on this LSI. If the NMIF bit was set before the transfer, the DMATCR indicates
the transfer count that has been specified. If the NMIF bit was set during the transfer, when
the DE bit is 1 and the TE bit is 0 in CHCR, the DMATCR indicates the number of
transfers remaining.
Also, the next addresses to be accessed can be found by reading SAR and DAR.
If the AE bit has been set, an address error has occurred. Check the settings in CHCR,
SAR, and DAR.
Usage Notes
Rev. 2.00 Feb. 12, 2010 Page 485 of 1330
REJ09B0554-0200