HD6417760BL200AV Renesas Electronics America, HD6417760BL200AV Datasheet - Page 1107

• Manufacturer Part Number: HD6417760BL200AV
• Description: SH4 7760, 17 X17 256BGA, LCDC, U
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417760BL200AV

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: Audio Codec, CAN, EBI/EMI, FIFO, I²C, MFI, MMC, SCI, Serial Sound, SIM, SPI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 69
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

28.2
The H-UDI contains two separate TAP controllers: one for controlling the boundary-scan function
and another for controlling the H-UDI reset and interrupt functions. Assertion of TRST, for
example at power-on reset, activates the boundary-scan TAP controller and enables the boundary-
scan function prescribed in the JTAG standards. Executing a switchover command to the H-UDI
allows usage of the H-UDI reset and H-UDI interrupts. This LSI, however, has the following
limitations:
• Clock-related pins (EXTAL, XTAL, and CKIO) are out of the scope of the boundary-scan test.
• Reset-related pins (RESET, MRESET, and CA) are out of the scope of the boundary-scan test.
• H-UDI-related pins (TCK, TDI, TDO, TMS, TRST, and ASEBRK/BRKACK) are out of the
• Analog pins (AN0 to AN3, USB_DM, and USB_DP) are out of the scope of the boundary-
• I
• To perform EXTEST, assert MRESET pin low, negate the RESET pin high and assert the CA
• To perform the boundary scan (EXTEST, SAMPLE/PRELOAD, or BYPASS), supply a clock
• During the boundary scan (EXTEST, SAMPLE/PRELOAD, and BYPASS), the maximum
• The external controller has 3-bit access to the boundary-scan TAP controller via the H-UDI.
Table 28.2 shows the commands supported by the boundary-scan TAP controller.
scope of the boundary-scan test.
scan test.
boundary-scan test.
pin low. To perform SAMPLE/PRELOAD, assert the CA pin high and negate the RESET pin
low.
signal to the EXTAL pin and perform a power-on reset with the RESET pin. The input clock
frequency should be in the range of 1 to 34 MHz. Perform the boundary scan after the power-
on oscillation settling time (t
may be suspended after t
section 33, Electrical Characteristics.
TCK signal frequency is 2 MHz.
2
C pins (I2C0_SDA, I2C0_SCL, I2C1_SDA, and I2C1_SCL) are out of the scope of the
Boundary Scan TAP Controllers (EXTEST, SAMPLE/PRELOAD,
and BYPASS)
OSC1
has elapsed. For details of power-on oscillation settling time, see
OSC1
) has elapsed. The supply of a clock signal to the EXTAL pin
Rev. 2.00 Feb. 12, 2010 Page 1023 of 1330
REJ09B0554-0200