HD6417760BL200AV Renesas Electronics America, HD6417760BL200AV Datasheet - Page 1022

• Manufacturer Part Number: HD6417760BL200AV
• Description: SH4 7760, 17 X17 256BGA, LCDC, U
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417760BL200AV

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: Audio Codec, CAN, EBI/EMI, FIFO, I²C, MFI, MMC, SCI, Serial Sound, SIM, SPI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 69
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Register Name
Response register 8
Response register 9
Response register 10
Response register 11
Response register 12
Response register 13
Response register 14
Response register 15
Response register 16
Data timeout register
Data register
FIFO pointer clear register
DMA control register
Interrupt control register 2
Interrupt status register 2
Receive data timing select register
Command register 0
Command register 1
Command register 2
Command register 3
Command register 4
Command register 5
Command start register
Operation control register
Card status register
Table 26.2 Register Configuration (2)
Register Name
Rev. 2.00 Feb. 12, 2010 Page 938 of 1330
REJ09B0554-0200
Abbrev.
RSPR8
RSPR9
RSPR10
RSPR11
RSPR12
RSPR13
RSPR14
RSPR15
RSPR16
DTOUTR
DR
FIFOCLR
DMACR
INTCR2
INTSTR2
RDTIMSEL R/W
CMDR0
CMDR1
CMDR2
CMDR3
CMDR4
CMDR5
CMDSTRT H'00
OPCR
CSTR
Abbrev.
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
W
R/W
R/W
R/W
H'00
H'00
H'00
H'00
H'00
H'00
H'00
H'0x
Power-on
Reset by
RESET
Pin/WDT/
H-UDI
P4 Address
H'FE50 0028
H'FE50 0029
H'FE50 002A
H'FE50 002B
H'FE50 002C
H'FE50 002D
H'FE50 002E
H'FE50 002F
H'FE50 0030
H'FE50 0032
H'FE50 0040
H'FE50 0042
H'FE50 0044
H'FE50 0046
H'FE50 0048
H'FE50 004A
Manual Reset
by RESET
Pin/WDT/
Multiple
Exception
H'00
H'00
H'00
H'00
H'00
H'00
H'00
H'00
H'0x
Area 7 Address Size
H'1E50 0028
H'1E50 0029
H'1E50 002A
H'1E50 002B
H'1E50 002C
H'1E50 002D
H'1E50 002E
H'1E50 002F
H'1E50 0030
H'1E50 0032
H'1E50 0040
H'1E50 0042
H'1E50 0044
H'1E50 0046
H'1E50 0048
H'1E50 004A
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Sleep
by Sleep
Instruction/
Deep Sleep
by
Hardware
8
8
8
8
8
8
8
8
8
16
16
8
8
8
8
8
*
Standby
by
Software/
Each
Module
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Sync
Clock
Pck
Pck
Pck
Pck
Pck
Pck
Pck
Pck
Pck
Pck
Pck
Pck
Pck
Pck
Pck
Pck