HD6417760BL200AV Renesas Electronics America, HD6417760BL200AV Datasheet - Page 914

• Manufacturer Part Number: HD6417760BL200AV
• Description: SH4 7760, 17 X17 256BGA, LCDC, U
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417760BL200AV

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: Audio Codec, CAN, EBI/EMI, FIFO, I²C, MFI, MMC, SCI, Serial Sound, SIM, SPI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 69
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

• CANTXACK0
Initial value:
Note: * Only a write of 1 only is allowed to clear the bit.
22.5.10 Abort Acknowledge Registers 1 and 0 (CANABACK1, CANABACK0)
The CANABACK registers are two 16-bit read/conditionally-write registers that are used to signal
to the CPU that a mailbox transmission has been aborted as per its each request. When an abort
has succeeded, the HCAN2 sets the corresponding bit in CANABACK. The host CPU may clear
the Abort Acknowledge bit by writing a 1 to the corresponding bit. Writing a 0 has no effect. A
CANABACK bits position is set by the HCAN2 to acknowledge that a CANTXPR bit has been
cleared by the corresponding CANTXCR bit.
• CANABACK1
Initial value:
Rev. 2.00 Feb. 12, 2010 Page 830 of 1330
REJ09B0554-0200
Bit
15 to 1
0
R/W:
R/W:
Bit:
Bit:
TXACK0
ABACK1
Bit Name
TXACK0[15:1]
⎯
R/W*
R/W*
_15
_15
15
15
0
0
TXACK0
ABACK1
R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W*
R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W*
_14
_14
14
14
0
0
TXACK0
ABACK1
_13
_13
13
13
0
0
ABACK1
TXACK0
Initial Value
All 0
0
_12
_12
12
12
0
0
ABACK1
TXACK0
_11
_11
11
11
0
0
TXACK0
ABACK1
_10
_10
10
10
0
0
R/W
R/W*
R
TXACK0
ABACK1
_9
_9
9
0
9
0
TXACK0
ABACK1
_8
_8
8
0
8
0
Description
Notifies that requested transmission of the
corresponding Mailbox has been finished
successfully. Bits 15 to 1 correspond to
Mailboxes 15 to 1 respectively.
0: Clearing condition: Write a 1 to this bit.
1: The corresponding Mailbox has
Reserved
This bit is always 0 as this Mailbox is receive-
only. Writing a 1 to this bit has no effect. This
bit is always read as 0.
ABACK1
TXACK0
successfully transmitted messages
(Data or Remote Frame).
Setting condition: Completion of message
transmission for the corresponding Mailbox
_7
_7
7
0
7
0
ABACK1
TXACK0
_6
_6
0
0
6
6
TXACK0
ABACK1
_5
_5
5
0
5
0
TXACK0
ABACK1
_4
_4
4
0
4
0
TXACK0
ABACK1
_3
_3
3
0
3
0
ABACK1
TXACK0
2
_2
0
2
_2
0
TXACK0
ABACK1
_1
_1
1
0
1
0
ABACK1
_0
R
0
0
0
0
-