HD6417760BL200AV Renesas Electronics America, HD6417760BL200AV Datasheet - Page 1108

• Manufacturer Part Number: HD6417760BL200AV
• Description: SH4 7760, 17 X17 256BGA, LCDC, U
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417760BL200AV

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: Audio Codec, CAN, EBI/EMI, FIFO, I²C, MFI, MMC, SCI, Serial Sound, SIM, SPI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 69
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Table 28.2 Commands Supported by Boundary-Scan TAP Controller
28.2.1
SDBSR is a shift register, located on the PAD, for controlling the input/output pins.
Using the EXTEST and SAMPLE/PRELOAD commands, a boundary-scan test complying with
the JTAG standards (IEEE1149.1) can be carried out. Table 28.3 shows the correspondence
between pins of this LSI and the SDBSR values.
Table 28.3 SDBSR Configuration
Rev. 2.00 Feb. 12, 2010 Page 1024 of 1330
REJ09B0554-0200
Bit 2
0
0
0
Other than above
Bit
499
498
497
496
495
494
493
492
491
490
489
488
487
486
485
484
483
482
481
Abbreviation
From TDI
SCIF2_TXD
SCIF2_TXD
SCIF2_TXD
SCIF1_CLK
SCIF1_CLK
SCIF1_CLK
SCIF2_CLK
SCIF2_CLK
SCIF2_CLK
NMI
NMI
NMI
CMT_CTR3
CMT_CTR3
CMT_CTR3
CMT_CTR2
CMT_CTR2
CMT_CTR2
CMT_CTR1
Boundary Scan Register (SDBSR)
Bit 1
0
0
1
Bit 0
0
1
1
I/O*
IN
OUT
Control
IN
OUT
Control
IN
OUT
Control
IN
OUT
Control
IN
OUT
Control
IN
OUT
Control
IN
Description
EXTEST
SAMPLE/PRELOAD
H-UDI (switchover command)
BYPASS mode
Bit
480
479
478
477
476
475
474
473
472
471
470
469
468
467
466
465
464
463
462
461
Abbreviation
CMT_CTR1
CMT_CTR1
CMT_CTR0/TCLK
CMT_CTR0/TCLK
CMT_CTR0/TCLK
STATUS1
STATUS1
STATUS1
HSPI_CLK
HSPI_CLK
HSPI_CLK
HSPI_CS
HSPI_CS
HSPI_CS
HSPI_TX
HSPI_TX
HSPI_TX
HSPI_RX
HSPI_RX
HSPI_RX
I/O*
OUT
Control
IN
OUT
Control
IN
OUT
Control
IN
OUT
Control
IN
OUT
Control
IN
OUT
Control
IN
OUT
Control