HD6417760BL200AV Renesas Electronics America, HD6417760BL200AV Datasheet - Page 1038

• Manufacturer Part Number: HD6417760BL200AV
• Description: SH4 7760, 17 X17 256BGA, LCDC, U
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417760BL200AV

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: Audio Codec, CAN, EBI/EMI, FIFO, I²C, MFI, MMC, SCI, Serial Sound, SIM, SPI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 69
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

26.3.11 Card Status Register (CSTR)
CSTR indicates the MMCIF status during command sequence execution.
Rev. 2.00 Feb. 12, 2010 Page 954 of 1330
REJ09B0554-0200
Bit
15 to 0
Bit
7
6
5
Bit
Name
BUSY
FIFO_
FULL
FIFO_
EMPTY
Bit
Name
DTOUTR
Initial value:
Initial
Value
0
0
0
Initial
Value
All 1
R/W:
Bit:
R/W
R
R
R
BUSY
R
7
0
R/W
R/W
FIFO_
FULL
6
0
R
Description
Indicates command execution status. When the CMDOFF
bit in OPCR is set to 1, this bit is cleared to 0 because the
MMCIF command sequence is aborted.
0: Idle state waiting for a command, or data busy state
1: Command sequence execution in progress
FIFO Full
This bit is set to 1 when the FIFO becomes full while data
is being received from the card, and cleared to 0 when
RD_CONTI is set to 1 or the command sequence is
completed.
Indicates whether the FIFO is empty or not.
0: The FIFO is empty.
1: The FIFO is full.
FIFO Empty
This bit is set to 1 when the FIFO becomes empty while
data is being sent to the card, and cleared to 0 when
DATA_EN is set to 1 or the command sequence is
completed.
Indicates whether the FIFO holds data or not.
0: The FIFO includes data.
1: The FIFO is empty.
Command Busy
EMPTY
Description
Data Timeout Time/10,000
Data timeout time: Peripheral clock cycle x DTOUTR
setting value x 10,000.
FIFO_
R
5
0
CWRE
4
0
R
DTBUSY
R
3
0
DTBUSY
_TU
2
R
-
R
0
1
-
REQ
R
0
0