HD6417760BL200AV Renesas Electronics America, HD6417760BL200AV Datasheet - Page 998

• Manufacturer Part Number: HD6417760BL200AV
• Description: SH4 7760, 17 X17 256BGA, LCDC, U
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417760BL200AV

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: Audio Codec, CAN, EBI/EMI, FIFO, I²C, MFI, MMC, SCI, Serial Sound, SIM, SPI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 69
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

To place the off-chip codec device into the power-down mode, write 1 to bit 12 of the register
index 26 in the off-chip codec via the HAC. When entering the power-down mode, the off-chip
codec stops HAC_BIT_CLK and suspends the normal operation. The off-chip codec acts in the
same manner at power-on. To resume the normal operation, perform a cold reset or a warm reset
on the off-chip codec.
25.3.2
HACCSAR is a 32-bit read/write register that specifies the address of the codec register to be read
/written. When requesting a write to/read from a codec register, write the command register
address to HACCSAR. Then the HAC transmits this register address to the codec via slot 1.
After the codec has responded to a read request (HACRSR.STARY = 1), the status address
received via slot 1 can be read out from HACCSAR.
Initial value:
Initial value:
Rev. 2.00 Feb. 12, 2010 Page 914 of 1330
REJ09B0554-0200
Bit
Bit
8 to 6
5
4 to 0
R/W:
R/W:
Bit:
Bit:
Bit Name
Bit Name
⎯
ST
⎯
Command/Status Address Register (HACCSAR)
CA3/
SA3
R/W
31
15
R
0
0
-
CA2/
SA2
R/W
30
14
-
R
0
0
CA1/
SA1
R/W
29
13
R
0
0
-
Initial Value
Initial Value
All 0
0
All 0
CA0/
SA0
R/W
28
12
R
0
0
-
EQ3
SLR
27
11
R
R
0
0
-
SLR
EQ4
R/W
R/W
R
W
R
26
10
R
R
-
0
0
SLR
EQ5
25
R
R
-
0
9
0
Description
Description
Reserved
Always 0 for read and write.
Start Transfer
[Write]
1: Starts data transmission/reception.
0: Stops data transmission/reception at the end of
[Read access]
Always read as 0.
Reserved
Always 0 for read and write.
EQ6
SLR
24
R
R
0
8
0
-
the current frame. Do not take this action to
terminate transmission/reception in normal
operation.
EQ7
SLR
23
R
R
0
7
0
-
SLR
EQ8
22
R
R
0
0
6
-
SLR
EQ9
21
R
R
0
5
0
-
EQ10
SLR
20
R
R
0
4
0
-
EQ11
R/W
RW
SLR
19
R
0
3
0
EQ12
CA6/
R/W
SA6
SLR
18
R
0
2
0
CA5/
SA5
R/W
17
R
0
1
-
0
CA4/
SA4
R/W
16
R
0
0
0
-