HD6417760BL200AV Renesas Electronics America, HD6417760BL200AV Datasheet - Page 1178

• Manufacturer Part Number: HD6417760BL200AV
• Description: SH4 7760, 17 X17 256BGA, LCDC, U
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417760BL200AV

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: Audio Codec, CAN, EBI/EMI, FIFO, I²C, MFI, MMC, SCI, Serial Sound, SIM, SPI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 69
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

It is also possible for the user to set the color palette when necessary, according to the procedure
below.
1. The PALEN bit in the LDPALCR is 0 (initial value); normal display operation
2. Access LDPALCR and set the PALEN bit to 1; enter color-palette setting mode after three
3. Access LDPALCR and confirm that the PALS bit is 1.
4. Access LDPR00 to LDPRFF and write the required values to the PALD00 to PALDFF bits.
5. Access LDPALCR and clear the PALEN bit to 0; return to normal display mode after a cycle
While the PALS bit in LPDALCR is set to 1, the display data for the LCDC (LCD_DATA) will
output a value of 0.
PALDnn color and gradation data should be set as above.
For a color display, PALDnn [23:16], PALDnn [15:8], and PALDnn [7:0] respectively hold the R,
G, and B data. However, although there are register bits at PALDnn [18:16], PALDnn [9:8], and
PALDnn [2:0], there is no corresponding memory for them. PALDnn [18:16], PALDnn [9:8], and
PALDnn [2:0] are thus not available for storing palette data. The numbers of valid bits are thus R:
5, G: 6, and B: 5. However, 24-bit (R: 8 bits, G: 8 bits, and B: 8 bits) data should be written to the
palette-data registers. When the values for PALDnn [23:19], PALDnn [15:10], or PALDnn [7:3]
are not 0, 1 or 0 should be written to PALDnn [18:16], PALDnn [9:8], or PALDnn [2:0],
respectively. When the values of PALDnn [23:19], PALDnn [15:10], or PALDnn [7:3] are 0, 0
should be written to PALDnn [18:16], PALDnn [9:8], or PALDnn [2:0], respectively. Data is thus
extended to 24 bits.
Grayscale data for a monochromatic display should be set in PALDnn [7:3]. PALDnn [23:8] are
all "don't care". When the value in PALDnn [7:3] is not 0, 1s should be written to PALDnn [2:0].
When the value in PALDnn [7:3] is 0, 0s should be written to PALDnn [2:0]. Data is thus
extended to 8 bits.
Rev. 2.00 Feb. 12, 2010 Page 1094 of 1330
REJ09B0554-0200
Color
Monochrome
cycles of peripheral clock.
of peripheral clock.
31
Figure 30.3 Color-Palette Data Format
R7
23
R6
R5
R4
R3
R2
R1
R0
G7
15
G6
G5
G4
G3
G2
G1
G0
M7
B7
7
M6
B6
M5
B5
M4
B4
M3
B3
M2
B2
M1
B1
M0
B0
0