HD6417760BL200AV Renesas Electronics America, HD6417760BL200AV Datasheet - Page 733

• Manufacturer Part Number: HD6417760BL200AV
• Description: SH4 7760, 17 X17 256BGA, LCDC, U
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417760BL200AV

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: Audio Codec, CAN, EBI/EMI, FIFO, I²C, MFI, MMC, SCI, Serial Sound, SIM, SPI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 69
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

18.4.2
Table 18.3 shows a map of the bits in the registers used by the smart card interface.
Set 0 or 1 to a bit if indicated as 0 or 1 in the following table. Set a bit without 0/1 indication
according to below instructions.
Table 18.3 Register Settings for the Smart Card Interface
(1) Se
When the IC card is set for the direct convention, the O/E bit is set to 0; for the inverse
convention, it is set to 1.
(2) Bit rate register (SIBRR) setting
Sets the bit rate. For the method of computing settings, refer to section 18.4.3, Clocks.
(3) Serial control register (SISCR) settings
The different interrupts can be enabled and disabled using the TIE, RIE, TEIE, and WAIT_IE bits.
By setting either the TE or RE bit to 1, transmission or reception is selected.
The CKE1 and CKE0 bits are used to select the clock output state. For details, refer to section
18.4.3, Clocks.
Register
SISMR
SIBRR
SISCR
SITDR
SISSR
SIRDR
SISCMR
SISC2R
SIWAIT
SIGRD
SISMPL
r
ial mode register (SISMR) setting
Register Settings
Bit 7
0
0
TIE
TDRE
0
EIO
Bit 6
0
0
RIE
RDRF
LCB
0
SISCMPL[10:0] (16-bit register, but bits 15 to 11 are 0)
PE
0
Bit 5
TE
ORER
PB
0
SIWAIT[15:0] (16-bit register)
Bit 4
O/E
0
RE
ERS
0
0
SIGRD[7:0]
SIRD[7:0]
SITD[7:0]
Bit 3
0
0
WAIT_IE
PER
SDIR
0
Bit
Rev. 2.00 Feb. 12, 2010 Page 649 of 1330
Bit 2
0
BRR2
TEIE
TEND
SINV
0
Bit 1
0
BRR1
CKE1
WAIT_ER
RST
0
REJ09B0554-0200
Bit 0
0
BRR0
CKE0
0
0
SMIF