HD6417760BL200AV Renesas Electronics America, HD6417760BL200AV Datasheet - Page 19

• Manufacturer Part Number: HD6417760BL200AV
• Description: SH4 7760, 17 X17 256BGA, LCDC, U
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417760BL200AV

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: Audio Codec, CAN, EBI/EMI, FIFO, I²C, MFI, MMC, SCI, Serial Sound, SIM, SPI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 69
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Item
19.4.8 Master
Transmit Operation
(Single Buffer Mode)
19.5.1 Master
Transmitter Operation
(FIFO Buffer Mode)
19.6.1 Master
Transmitter (Single
Buffer Mode)
(4) Monitor the
progress of data byte
transmission:
19.6.4 Master
Transmitter (FIFO
Buffer Mode)
Page
693
697, 698 Description amended
699
702
Revision (See Manual for Details)
Description amended
This section describes the transmit procedure and operations
in master transmit mode. Figures 19.9 to 19.11 are the timing
charts in master transmit mode. Setting the MDBS bit to 1 in
the master control register has the I2C module enter single
buffer mode.
1. For initial setting, set clock control bits in the clock control
Notes:
2. FSB must be set to 1 at least one SCL clock cycle after the
Note: * If FSB is not set with this timing, the stop condition (P)
Description amended
(a) Wait for a master event (the MDE bit in the master status
(b) Load the next data byte into the transmit data register.*
Note: * There is no need to observe the limitation that
Description amended
8. Set FSB to 1 after 1 SCL clock period has completed and
register and interrupt generation bits in the master interrupt
enable register, according to the slave address, transmit
data, and the transmit speed. Since the slave mode is also
required even when only the master mode is used, set the
device address to the slave address register.
Do not modify either the master control register MDBS bit
or the slave control register SDBS bit during operation.
Incorrect operation may occur if these bits are changed
during operation.
before 9 SCL clock periods have completed after TDFE was
set to 1.
(See figure 19.15)
transmit FIFO data empty flag (TDFE) is set, and within 9
SCL clock cycles following that flag being set. (See figure
19.15.)* For example, to transfer 3 bytes of data, after 3
bytes of data have been written to the FIFO and transferred,
verify that TDFE = 1 either by poling or with the transmit
FIFO data empty (TXI) interrupt and then set FSB after the
first SCL clock cycle and before the ninth SCL clock cycle
completes following TDFE being set to 1. Note that care is
required concerning the timing with which FSB is set in
application system, in particular, check the interrupt
response and handling times carefully.
register).
"execution must continue until the first data byte has
been output" in this case.
may not be issued correctly.
Rev. 2.00 Feb. 12, 2010 Page xvii of lxxxii
REJ09B0554-0200