HD6417760BL200AV Renesas Electronics America, HD6417760BL200AV Datasheet - Page 552

• Manufacturer Part Number: HD6417760BL200AV
• Description: SH4 7760, 17 X17 256BGA, LCDC, U
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417760BL200AV

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: Audio Codec, CAN, EBI/EMI, FIFO, I²C, MFI, MMC, SCI, Serial Sound, SIM, SPI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 69
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Section 11 Direct Memory Access Controller (DMAC)
Resetting the DMABRG makes the following register values undefined.
• DMAATXSAR(0/1)
• DMAARXDAR(0/1)
• DMAATXTCR(0/1)
• DMAARXTCR(0/1)
• DMAATXTCNT(0/1)
• DMAARXTCNT(0/1)
Do not access the registers of the HAC, SSI, USB, LCDC, and DMAC (except for DMAPCR)
while the BRGRST bit is 1. Operation is not guaranteed when these registers are accessed in this
state.
Note: * Make sure to write 1 to the CHSET bit in CHCR0 before re-specifying the DMAC
registers in the case of DMAC reactivation (DMA transfer will be resumed).
11.6.3
DMA Transfer Operating Mode for HAC and SSI
This LSI has two audio codec interfaces. The HAC and SSI are assigned to the audio codec
interfaces. This assignment is selected by the IPSELR11 and IPSELR10 bits in IPSELR of the
PFC. For details see section 24.2.35, Peripheral Module Select Register (IPSELR).
Figure 11.31 shows a configuration of the DMA for the HAC and SSI. This LSI transfers data by
the DMA transfer request from the audio codec via DMAC channel 0. A transfer between
synchronous DRAM and the audio codec is performed by using a 32-byte 2-stage FIFO for each
interface.
Audio data for transfer is stored in the transmit/receive buffer of the synchronous DRAM. The
transmit/receive buffer is defined by specifying the start address to DMAARXDAR or
DMAATXSAR and the number of transfer bytes to DMAARXTCR or DMAATXTCR.
When half of the data is transferred (A0TXH, A0RXH, A1TXH, or A1RXH interrupt is used) or
all data is transferred (A0TXE, A0RXE, A1TXE, or A1RXE interrupt is used), an interrupt can be
generated. Double buffer control for audio data can be used by switching halved transmit/receive
buffers.
DMAARXDAR, DMAATXSAR, DMAARXTCR, and DMAATXTCR have the auto-reload
function. When the same buffer is repeatedly used in the auto-reload function, it is not necessary
to re-specify the registers.
Rev. 2.00 Feb. 12, 2010 Page 468 of 1330
REJ09B0554-0200