HD6417760BL200AV Renesas Electronics America, HD6417760BL200AV Datasheet - Page 1225

• Manufacturer Part Number: HD6417760BL200AV
• Description: SH4 7760, 17 X17 256BGA, LCDC, U
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417760BL200AV

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: Audio Codec, CAN, EBI/EMI, FIFO, I²C, MFI, MMC, SCI, Serial Sound, SIM, SPI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 69
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

31.6
(1) Instruction Access Cycle Break Condition Settings
1. Register settings: BASRA = H'80 / BARA = H'0000 0404 / BAMRA = H'00 /
2. Register settings: BASRA = H'80 / BARA = H'0003 7226 / BAMRA = H'00 /
3. Register settings: BASRA = H'80 / BARA = H'0002 7128 / BAMRA = H'00 /
BBRA = H'0014 / BASRB = H'70 / BARB = H'0000 8010 / BAMRB = H'01 /
BBRB = H'0014 / BDRB = H'0000 0000 / BDMRB = H'0000 0000 / BRCR = H'0400
⎯ Conditions set: Independent channel A/channel B mode
A user break is generated after execution of the instruction at address H'0000 0404 with ASID
= H'80, or before execution of an instruction at addresses H'0000 8000 to H'0000 83FE with
ASID = H'70.
BBRA = H'0016 / BASRB = H'70 / BARB = H'0003 722E / BAMRB = H'00 /
BBRB = H'0016 / BDRB = H'00000000 / BDMRB = H'00000000 / BRCR = H'0008
⎯ Conditions set: Channel A → channel B sequential mode
The instruction at address H'0003 7266 with ASID = H'80 is executed, then a user break is
generated before execution of the instruction at address H'0003 722E with ASID = H'70.
BBRA = H'001A / BASRB = H'70 / BARB = H'0003 1415 / BAMRB = H'00 /
BBRB = H'0014 / BDRB = H'0000 0000 / BDMRB = H'0000 0000 / BRCR = H'0000
⎯ Conditions set: Independent channel A/channel B mode
• Channel A: ASID: H'80 / address: H'0000 0404 / address mask: H'00
• Channel B: ASID: H'70 / address: H'0000 8010 / address mask: H'01
• Channel A: ASID: H'80 / address: H'0003 7226 / address mask: H'00
• Channel B: ASID: H'70 / address: H'0003 722E / address mask: H'00
• Channel A: ASID: H'80 / address: H'0002 7128 / address mask: H'00
• Channel B: ASID: H'70 / address: H'0003 1415 / address mask: H'00
Examples of Use
Bus cycle: instruction access (post-instruction-execution), read (operand size not
included in conditions)
Data: H'0000 0000 / data mask: H'0000 0000
Bus cycle: instruction access (pre-instruction-execution), read (operand size not
included in conditions)
Bus cycle: instruction access (pre-instruction-execution), read, word
Data: H'0000 0000 / data mask: H'0000 0000
Bus cycle: instruction access (pre-instruction-execution), read, word
Bus cycle: CPU, instruction access (pre-instruction-execution), write, word
Data: H'0000 0000 / data mask: H'0000 0000
Rev. 2.00 Feb. 12, 2010 Page 1141 of 1330
REJ09B0554-0200