HD6417760BL200AV Renesas Electronics America, HD6417760BL200AV Datasheet - Page 741

• Manufacturer Part Number: HD6417760BL200AV
• Description: SH4 7760, 17 X17 256BGA, LCDC, U
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417760BL200AV

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: Audio Codec, CAN, EBI/EMI, FIFO, I²C, MFI, MMC, SCI, Serial Sound, SIM, SPI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 69
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

18.5.2
Figure 18.8 shows repetition operations when the smart card interface is in receiver mode. (1) to
(5) in figure 18.8 correspond to items 1 to 5 described below.
1. If checking of the received parity bit detects an error, the PER bit in SISSR is automatically set
2. The RDRF bit in SISSR is not set for frames in which a parity error occurs.
3. If checking of the received parity bit detects no error, the PER bit in SISSR is not set.
4. If checking of the received parity bit detects no error, it is assumed that reception was
5. If a normal frame is received, the pin is maintained in a high-impedance state at the timing for
Synchronization
sampling timing
RDRF
PER
Received data
to 1. If the RIE bit in SISCR is set for enable, an SIMERI request is issued. The PER bit in
SISSR should be cleared to 0 before the sampling timing for the next parity bit.
completed normally, and the RDRF bit in SISSR is automatically set to 1. If the RIE bit in
SISCR is 1 and the EIO bit is 0, an SIMRXI request is generated.
transmission of error signals.
Data sampling
timing
Serial clock
(SIM_CLK)
Repetition when the Smart Card Interface Is in Receiver Mode (T = 0)
Ds
Figure 18.8 Repetition in the Smart Card Interface Receiver Mode
D0 D1 D2 D3 D4 D5 D6 D7 DP
Figure 18.7 Received Data Sampling Timing in Smart Card Mode
0
186 clock pulses
nth transfer frame
Start bit
372 clock pulses
185
DE
(1)
(2)
Ds
371
D0 D1 D2 D3 D4 D5 D6 D7 DP
0
Repeat frame
Rev. 2.00 Feb. 12, 2010 Page 657 of 1330
D0
185
(5)
(4)
(3)
(DE)
Ds
n + 1th transfer frame
D0 D1 D2 D3 D4
REJ09B0554-0200
371
0
D1