HD6417760BL200AV Renesas Electronics America, HD6417760BL200AV Datasheet - Page 78

• Manufacturer Part Number: HD6417760BL200AV
• Description: SH4 7760, 17 X17 256BGA, LCDC, U
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417760BL200AV

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: Audio Codec, CAN, EBI/EMI, FIFO, I²C, MFI, MMC, SCI, Serial Sound, SIM, SPI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 69
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Section 7 Caches
Table 7.1
Table 7.2
Table 7.3
Table 7.4
Table 7.4
Section 8 Exceptions
Table 8.1
Table 8.2
Table 8.2
Section 9 Interrupt Controller (INTC)
Table 9.1
Table 9.2
Table 9.2
Table 9.3
Table 9.4
Table 9.5
Table 9.5
Table 9.6
Table 9.7
Table 9.8
Section 10 Bus State Controller (BSC)
Table 10.1
Table 10.2
Table 10.3
Table 10.4
Table 10.5
Table 10.6
Table 10.6
Table 10.7
Table 10.8
Table 10.9
Table 10.10 32-Bit Off-chip Device/Big-Endian Access and Data Alignment.......................... 299
Table 10.11 16-Bit Off-chip Device/Big-Endian Access and Data Alignment.......................... 300
Table 10.12 8-Bit Off-chip Device/Big-Endian Access and Data Alignment............................ 301
Table 10.13 32-Bit Off-Chip Device/Little-Endian Access and Data Alignment ...................... 302
Table 10.14 16-Bit Off-Chip Device/Little-Endian Access and Data Alignment ...................... 303
Table 10.15 8-Bit Off-Chip Device/Little-Endian Access and Data Alignment ........................ 304
Rev. 2.00 Feb. 12, 2010 Page lxxvi of lxxxii
REJ09B0554-0200
Cache Features (EMODE = 0) ............................................................................... 151
Cache Features (EMODE = 1) ............................................................................... 151
Store Queue Features ............................................................................................. 152
Register Configuration (1)...................................................................................... 155
Register Configuration (2)...................................................................................... 155
Exception Sources and Priorities............................................................................ 185
Register Configuration (1)...................................................................................... 192
Register Configuration (2)...................................................................................... 192
Pin Configuration ................................................................................................... 223
Register Configuration (1)...................................................................................... 223
Register Configuration (2)...................................................................................... 224
Interrupt Request Sources and IPRA to IPRD........................................................ 226
Interrupt Request Sources and INTPRI00 to INTPRI0C ....................................... 227
Interrupt Request Sources and Bit Assignments in Each Register (1) ................... 230
Interrupt Request Sources and Bit Assignments in Each Register (2) ................... 231
IRL3 to IRL0 Pins and Interrupt Levels................................................................. 236
Interrupt Exception Handling Sources and Priority Order ..................................... 239
Interrupt Response Time ........................................................................................ 246
Pin Configuration ................................................................................................... 250
Off-chip Memory Space Map................................................................................. 253
Correspondence between Off-chip Pins (MD4 and MD3) and Bus Width ............ 254
PCMCIA Interface Features................................................................................... 255
PCMCIA Support Interfaces .................................................................................. 255
Register Configuration (1)...................................................................................... 258
Register Configuration (2)...................................................................................... 259
Idle Insertion between Accesses............................................................................. 273
MPX Interface Setting............................................................................................ 280
WCR3 and WCR4 Settings for Area 1................................................................... 283