HD6417760BL200AV Renesas Electronics America, HD6417760BL200AV Datasheet - Page 765

SH4 7760, 17 X17 256BGA, LCDC, U

HD6417760BL200AV

Manufacturer Part Number
HD6417760BL200AV
Description
SH4 7760, 17 X17 256BGA, LCDC, U
Manufacturer
Renesas Electronics America
Series
SuperH® SH7750r
Datasheet

Specifications of HD6417760BL200AV

Core Processor
SH-4
Core Size
32-Bit
Speed
200MHz
Connectivity
Audio Codec, CAN, EBI/EMI, FIFO, I²C, MFI, MMC, SCI, Serial Sound, SIM, SPI, USB
Peripherals
DMA, LCD, POR, WDT
Number Of I /o
69
Program Memory Type
ROMless
Ram Size
48K x 8
Voltage - Supply (vcc/vdd)
1.4 V ~ 1.6 V
Data Converters
A/D 4x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
256-BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-

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Manufacturer
Quantity
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Part Number:
HD6417760BL200AV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Part Number:
HD6417760BL200AV
Manufacturer:
RENENAS
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• Transmit Data Register (ICTXD) (Single Buffer Mode)
Initial value:
Initial value:
When the FIFO buffer is selected by the SDBS bit of ICSCR or the MDBS bit of ICMCR, the
operation is as follows:
• Receive Data Register (ICRXD) (FIFO Buffer Mode)
Initial value:
Initial value:
Bit
31 to 8
7 to 0
ICRXD is a 16-stage FIFO register for storing the receive data. When 1-byte data is received,
the receive data is transferred to ICRXD from the shift register, and reception ends. After that,
the ICRXD is ready to receive and consecutive receive operations of up to 16 bytes of data are
possible. When 16 bytes of receive data are stored, the FIFO receive register is full.
ICRXD is read only and cannot be written to by the CPU. When the receive FIFO register is
completely empty, reading ICRXD will return an undefined value. When the receive FIFO
register is full, the subsequent data is lost.
R/W:
R/W:
R/W:
R/W:
Bit:
Bit:
Bit:
Bit:
Bit Name
TXD
31
15
31
15
R
R
R
R
0
0
-
-
-
-
-
-
30
14
30
14
R
R
R
R
-
-
-
-
-
-
0
0
29
13
29
13
R
R
R
R
0
0
-
-
-
-
-
-
Initial Value
All 0
All 0
28
12
28
12
R
R
R
R
0
0
-
-
-
-
-
-
27
11
27
11
R
R
R
R
0
0
-
-
-
-
-
-
R
R/W
R/W
26
10
26
10
R
R
R
R
-
0
-
0
-
-
-
-
25
25
R
R
R
R
-
0
9
-
0
-
-
9
-
-
Description
Reserved
These bits are always read as 0, and the write
value should always be 0.
Write Transmit Data
Data transmitted by master or slave.
24
24
R
R
R
R
0
8
0
8
-
-
-
-
-
-
R/W
23
23
R
R
R
0
7
0
7
-
-
-
-
Rev. 2.00 Feb. 12, 2010 Page 681 of 1330
R/W
22
22
R
R
R
0
0
6
6
-
-
-
-
R/W
21
21
R
R
R
0
5
0
5
-
-
-
-
R/W
20
20
Section 19 I
R
R
R
0
4
0
4
-
-
-
-
RXD
TXD
R/W
19
19
R
R
R
0
3
0
3
-
-
-
-
REJ09B0554-0200
R/W
18
18
R
R
R
0
2
0
2
-
-
-
-
2
C Bus Interface
R/W
17
17
R
R
R
0
1
0
1
-
-
-
-
R/W
16
16
R
R
R
0
0
0
0
-
-
-
-

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