HD6417760BL200AV Renesas Electronics America, HD6417760BL200AV Datasheet - Page 485

• Manufacturer Part Number: HD6417760BL200AV
• Description: SH4 7760, 17 X17 256BGA, LCDC, U
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417760BL200AV

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: Audio Codec, CAN, EBI/EMI, FIFO, I²C, MFI, MMC, SCI, Serial Sound, SIM, SPI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 69
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Bit
7 to 3
2
1
0
Bit Name
—
AE
NMIF
DME
Initial Value
All 0
0
0
0
R/W
R
R/W
R/W
R/W
Description
Reserved
These bits are always read as 0. The write value
should always be 0.
Address Error Flag
Indicates that an address error has occurred during
DMA transfer.
Setting this bit during data transfer will suspend
transfers on all channels and generate an interrupt
request (DMAE). The CPU cannot write 1 to this
bit. Write AE=0 after reading AE=1 to clear this bit.
0: No address error, DMA transfer enabled
[Clearing condition]
When 0 is written to the AE bit after reading AE = 1
1: Address error, DMA transfer disabled
[Setting condition]
When an address error is caused by the DMAC
NMI Flag
Indicates that NMI has been input. It is possible to
set this bit regardless of whether or not the DMAC
is operating. Setting this bit during data transfer will
suspend transfers on all channels. The CPU
cannot write 1 to this bit. Write NMIF=0 after
reading NMIF=1 to clear this bit.
0: No NMI input, DMA transfer enabled
[Clearing condition]
When 0 is written to NMIF after reading NMIF = 1
1: NMI input, DMA transfer disabled
[Setting condition]
When an NMI interrupt is generated
DMAC Master Enable
Enables activation of the entire DMAC. Setting the
DME bit and the DE bit in CHCR for the
corresponding channel to 1 will enable that
channel for translfer. Clearing this bit during data
transfer will suspend transfers on all channels.
Even if the DME bit has been set to 1, transfer is
not enabled when TE is 1 or DE is 0 in CHCR, or
when the NMIF or AE bit in DMAOR is 1.
0: Operation disabled on all channels
1: Operation enabled on all channels
Rev. 2.00 Feb. 12, 2010 Page 401 of 1330
REJ09B0554-0200