HD6417760BL200AV Renesas Electronics America, HD6417760BL200AV Datasheet - Page 267

• Manufacturer Part Number: HD6417760BL200AV
• Description: SH4 7760, 17 X17 256BGA, LCDC, U
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417760BL200AV

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: Audio Codec, CAN, EBI/EMI, FIFO, I²C, MFI, MMC, SCI, Serial Sound, SIM, SPI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 69
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

8.1
Exception handling processing is handled by a special routine, separate from normal program
processing, which is executed by the CPU in case of abnormal events. For example, if the
executing instruction ends abnormally, appropriate action must be taken in order to return to the
original program sequence, or report the abnormality before terminating the processing. The
process of generating an exception handling request in response to abnormal termination, and
passing control to a user-written exception handling routine, in order to support such functions, is
given the generic name of exception handling.
The SH-4 exception handling is of three kinds: for resets, general exceptions, and interrupts.
8.1.1
In exception handling, the contents of the program counter (PC), status register (SR), and R15 are
saved in the saved program counter (SPC), saved status register (SSR), and saved general
register15 (SGR), and the CPU starts execution of the appropriate exception handling routine
according to the vector address. An exception handling routine is a program written by the user to
handle a specific exception. The exception handling routine is terminated and control returned to
the original program by executing a return-from-exception instruction (RTE). This instruction
restores the PC and SR contents and returns control to the normal processing routine at the point at
which the exception occurred. The SGR contents are not written back to R15 with an RTE
instruction.
The basic processing flow is as follows.
1. The PC, SR, and R15 contents are saved in SPC, SSR, and SGR, respectively.
2. The block bit (BL) in SR is set to 1.
3. The mode bit (MD) in SR is set to 1.
4. The register bank bit (RB) in SR is set to 1.
5. In a reset, the FPU disable bit (FD) in SR is cleared to 0.
6. The exception code is written to bits 11 to 0 of the exception event register (EXPEVT) or
7. The CPU branches to the determined exception handling vector address, and the exception
interrupt event register (INTEVT).
handling routine begins.
Exception Handling Functions
Exception Handling Flow
Section 8 Exceptions
Rev. 2.00 Feb. 12, 2010 Page 183 of 1330
REJ09B0554-0200